Reduction Of Channel Length Research Articles

Edge-driven nanomembrane-based vertical organic transistors showing a multi-sensing capability

The effective utilization of vertical organic transistors in high current density applications demands further reduction of channel length (given by the thickness of the organic semiconducting layer and typically reported in the 100 nm range) along with the optimization of the source electrode structure. Here we present a viable solution by applying rolled-up metallic nanomembranes as the drain-electrode (which enables the incorporation of few nanometer-thick semiconductor layers) and by lithographically patterning the source-electrode. Our vertical organic transistors operate at ultra-low voltages and demonstrate high current densities (~0.5 A cm−2) that are found to depend directly on the number of source edges, provided the source perforation gap is wider than 250 nm. We anticipate that further optimization of device structure can yield higher current densities (~10 A cm−2). The use of rolled-up drain-electrode also enables sensing of humidity and light which highlights the potential of these devices to advance next-generation sensing technologies.

Directed Placement for mVLSI Devices

Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural “directedness” in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies.

Device Structure and Passivation Options for the Integration of Scaled IGZO TFTs

The focus of this work is on the performance dependence of scaled IGZO TFTs with variations in the device structure and semiconductor passivation scheme. TCAD simulation was used to provide insight on the details which establish the limits on electrostatic control. Dielectrics used for the gate and back-channel regions have been adjusted to overcome short-channel effects, along with required modifications in process recipes for PECVD passivation layers, oxygen ambient annealing, and ALD capping material. Scaled devices with channel lengths as small as L = 1 µm have been investigated and evaluated by the electrostatic behavior, and stability when subjected to thermal and bias stress. An optimized process and associated procedural details for scaled devices is presented, along with suggested options for further channel length reduction to submicron dimensions.

Impact of channel scaling on performance of single SiC nanowire UV photodetector

We have investigated the channel length dependence of the key performance parameters, such as speed, responsivity, external quantum efficiency (EQE), and responsivity–bandwidth product, of the silicon carbide nanowire-based ultraviolet (UV) photodetector devices with different channel lengths ranging from 120 to 800 nm. The device with the shortest channel length of 120 nm at low bias voltage of 0.5 V exhibited very high responsivity and EQE of 7.73 × 103 A / W and 7.77 × 104 % , respectively, under illumination to 254-nm UV light. Our experiments revealed that reduction in channel length resulted in significant enhancement in speed, responsivity, EQE, and responsivity–bandwidth product of the photodetector. This study suggests that scaling down in channel length could enable the development of high-speed and sensitive photodetector devices for emerging nanophotonic and nanoelectronic applications capable of operating at low voltages.

Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Improvement of contact resistance in flexible a-IGZO thin-film transistors by CF4/O2 plasma treatment

In this work, we analyze the effect of CF4/O2 plasma treatment on the contact interface between the amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) semiconductor and Titanium-Gold electrodes. First, the influence of CF4/O2 plasma treatment is evaluated using transmission line structures and compared to pure O2 and CF4 plasma, resulting in a reduction of the contact resistance RC by a factor of 24.2 compared to untreated interfaces. Subsequently, the CF4/O2 plasma treatment is integrated in the a-IGZO thin-film transistor (TFT) fabrication process flow. We achieve a reduction of the gate bias dependent RC by a factor up to 13.4, which results in an increased current drive capability. Combined with an associated channel length reduction, the effective linear field-effect mobility μlin,FE,eff is increased by up to 74.6% for the CF4/O2 plasma treated TFTs compared to untreated reference devices.

Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET

This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage

Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (Vth) roll-off, subthreshold swing (SS), and Ion/Ioff ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (Vth), subthreshold swing (SS), and Ion/Ioff ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more Ion/Ioff ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.

Non-Linear Self-Heating in Organic Transistors Reaching High Power Densities

The improvement of the performance of organic thin-film transistors is driven by novel materials and improved device engineering. Key developments are a continuous increase of the charge carrier mobility, a scale-down of transistor dimensions, and the reduction of contact resistance. Furthermore, new transistor designs such as vertical devices are introduced to benefit from drastically reduced channel length while keeping the effort for structuring moderate. Here, we show that a strong electrothermal feedback occurs in organic transistors, ultimately leading to output characteristics with regions of S-shaped negative differential resistance. For that purpose, we use an organic permeable-base transistor (OPBT) with outstanding current densities, where a strong and reproducible, non-linear electrothermal feedback is revealed. We derive an analytical description of the temperature dependent current-voltage behavior and offer a rapid investigation method for material systems, where a temperature-activated conductivity can be observed.

Study of Scaling of MOSFET on Various Electrical Characteristics using Silvaco TCAD Tool

MOSFETs are the driving work horse of semiconductor industry. Over the years, the MOSFET device density has been continuously increasing owing to the reduction in channel length of MOSFET device. This article discusses the effect of scaling i.e. channel length and gate oxide thickness on various parameters like threshold voltage, transconductance, maximum drain current and subthreshold slope. It is important to consider that with scaling of the channel length; the oxide thickness has to be scaled in the proportion which will cause the variation in the threshold voltage and transconductance. Scaling also results in variation in drain/source doping which affects the transconductance directly but has no effect on threshold voltage. The mechanism adopted in the current research work is the scaling of the channel length to study its impact on maximum drain current and subthreshold slope. The simulations of structures were performed using SILVACO TCAD tool. Keywords: Threshold voltage, sub-threshold leakage, scaling, SILVACO TCAD, Athena Cite this Article Prashant Kumar, Munish Vashistath, Bansal PK. Study of Scaling of MOSFET on Various Electrical Characteristics using Silvaco TCAD Tool. Journal of Semiconductor Devices and Circuits . 2018; 5(1): 11–19p.

Static and dynamic modeling of organic thin film transistors: effect of channel length on the Mayer–Neldel rule energy and quasistatic capacitances

In this work, pentacene based thin film transistors (TFTs) with different channel lengths (L = 2.5, 5, 10 and 20 μm) have been fabricated and characterized electrically. Exploiting the electrical characteristics, we have analyzed the channel length effect on the key parameters of fabricated TFTs. We found that the performance of pentacene-TFTs was enormously enhanced by the reduction of channel length .We have also examined the influence of contact and channel resistances (RCandRch) on the electrical proprieties of fabricated TFTs, using the transmission line method (TLM). Then, we have modeled the dependence of the total resistanceRTon the gate voltageVGusing the grain boundary trapping Meyer–Neldel rule (GBT-MNR) model and we have successfully reproduced, the output characteristic of pentacene TFTs using the overall resistance extracted from the GBT-MNR model. Finally, in order to investigate the channel length effect on the dynamic behavior of fabricated devices, we have reported a dynamic model based on the quasistatic assumptions which were used for metal-oxide-semiconductor field-effect transistor (MOSFET). Accordingly, we have presented a simple small-signal equivalent circuit to calculate theoretically the capacitances of pentacene-TFTs for different channel lengths.

An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage ( ${V}_{\text {th}}$ ) roll-off can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the ${V}_{\text {th}}$ roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.

Current controlled conveyor based on universal filter

Objectives: In the Current era, current conveyors become the most crucial design. In this paper, a multipurpose filter which acts as low pass, high pass, band pass, all pass and notch is presented. This design of multipurpose filter is based on DOCCCII. Methods/Statistical Analysis: The band width of the presented filter will depend on dc bias currents electronically. SPICE simulations of this multipurpose filter have been done using TSMC 0.35 μm CMOS process parameters. Findings: This filter circuit uses only two capacitors. The benefit of using this circuit is that it is electronically tunable. In these work different parameters of universal filter has been calculated and also simulated using CMOS process parameters. Application/Improvements: By making change in W/L ratios simulation results can be enhanced. Device can be made compact by reducing channel length and hence the power dissipation of device will be low and we can get better results.

Stability Behavior of Self-Aligned Coplanar a-IGZO Thin Film Transistors Fabricated by Deep Ultraviolet Irradiation

We fabricated self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs and defined the source/drain region using deep ultraviolet (DUV) irradiation. For our TFTs, source/drain region were well defined to designed dimensions and contact resistance was low value. The electrical properties of the device show field-effect mobility (μFE) of 13.2 cm2/Vs, subthreshold swing (S/S) of 0.32 V/decade, threshold voltage (Vth) of 3.2 V, and on/off ratio of 8.8 × 108, respectively. In addition, the reduced channel length (ΔL) and width-normalized contact resistance (RSDW) were 1.08 μm and 87.5 Ω cm, respectively. Stability behavior of self-aligned coplanar a-IGZO TFT fabricated by DUV irradiation was investigated under negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias temperature stress (PBTS). After the stress under NBS, NBIS, PBS, and PBTS, the Δ Vth values of −0.3 V, −0.8 V, 1.2 V, and 1.3 V were measured, respectively. Additionally, the electrical characteristics of the n+ doping region by DUV irradiation were not degraded under any of the stress conditions.

Current saturation and kink effect in zero-bandgap double-gate silicene field-effect transistors

Double gate silicene field effect transistor is investigated using Density Functional Theory (DFT) and Non-Equilibrium Green's Function (NEGF) formalism. The results suggest that with an increase in gate bias, bandgap is introduced in silicene which results in reduction in device current. The increase in silicene bandgap is also related to the reduction in channel length. It is observed that drain to source current (IDS) saturates on increasing drain to source voltage (VDS). On increasing VDS beyond saturation region, at some value of VDS kink effect is seen which is due to switching in the type of carriers at the drain end due to ambipolar channel. Transconductance (gm) is seen to reduce with reduction in channel length, however, gm improves with reduced oxide thickness due to better gate controllability. The output characteristics do not change much with oxide thickness.

Investigation of the drain-induced barrier lowering of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length

ABSTRACTThe transistor size needs to be reduced as the pixel density of the organic light-emitting diode (OLED) display increases for mobile application. Drain-induced barrier lowering (DIBL), however, hinders the further channel length reduction of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which leads to severe mura of the OLED display for the low-gray level. The two-dimensional device simulation analysis showed that the potential energy barrier for the holes in the p-channel TFT decreases as the drain voltage intensifies from −1 to −10 V. The barrier lowering becomes severe as the channel length is reduced from 5 to 2 µm, but it does not have any noticeable dependency on the grain size variation from 0.3 to 0.5 µm. It was also found that the degree of DIBL varies considerably depending on the position of the grain boundary even for the same grain size, as the channel length is reduced. It was determined from the analysis that was conducted in this study that the deviation of the subthreshold current for the variation of the grain size and the grain boundary location increases 64 times as the channel length is reduced from 5 to 2 µm.

P‐78: Calibration of a‐InGaZnO Thin Film Transistors with Various Channel Lengths using TCAD Simulation

We proposed the calibration procedure of a‐InGaZnO Thin Film Transistors (a‐IGZO TFTs) using Technology Computer Aided Design (TCAD) simulation. The various channel lengths of 5.2μm, 7.3μm, 30.3μm, 50.6μm, 81μm, and 152.2μm are fabricated and used for verifying the calibration results. The parameters of obtained from 152.2μm channel length TFT are applied to other devices with different channel lengths. From manufacturing point of view, we extracted the value of channel length reduction of TFTs from the output characteristics using TCAD simulation.

Ultra-low power FinFET-based domino circuits

ABSTRACTAggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.

The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

A new model to capture the physics of short channel double-gate junctionless transistor (DGJT) has been developed. By solving the 2-D Poisson’s equation, the channel potential solution is obtained for both the physical channel and the dynamic channel extension to the source and drain. This dynamic change in channel boundary in DGJT has a strong impact on the performance of junctionless transistor, especially at reduced channel length. Based on the channel potential solution, a smooth and continuous drain current model is derived from Pao–Sah’s dual integral. This model is valid for all operation modes, including full depletion, partial depletion, and accumulation. Extensive comparison with numerical simulation has been performed to validate model in both the long channel and short channel regimes.