Investigation of the drain-induced barrier lowering of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length

Abstract

ABSTRACTThe transistor size needs to be reduced as the pixel density of the organic light-emitting diode (OLED) display increases for mobile application. Drain-induced barrier lowering (DIBL), however, hinders the further channel length reduction of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which leads to severe mura of the OLED display for the low-gray level. The two-dimensional device simulation analysis showed that the potential energy barrier for the holes in the p-channel TFT decreases as the drain voltage intensifies from −1 to −10 V. The barrier lowering becomes severe as the channel length is reduced from 5 to 2 µm, but it does not have any noticeable dependency on the grain size variation from 0.3 to 0.5 µm. It was also found that the degree of DIBL varies considerably depending on the position of the grain boundary even for the same grain size, as the channel length is reduced. It was determined from the analysis that was conducted in this study that the deviation of the subthreshold current for the variation of the grain size and the grain boundary location increases 64 times as the channel length is reduced from 5 to 2 µm.