Abstract
The focus of this work is on the performance dependence of scaled IGZO TFTs with variations in the device structure and semiconductor passivation scheme. TCAD simulation was used to provide insight on the details which establish the limits on electrostatic control. Dielectrics used for the gate and back-channel regions have been adjusted to overcome short-channel effects, along with required modifications in process recipes for PECVD passivation layers, oxygen ambient annealing, and ALD capping material. Scaled devices with channel lengths as small as L = 1 µm have been investigated and evaluated by the electrostatic behavior, and stability when subjected to thermal and bias stress. An optimized process and associated procedural details for scaled devices is presented, along with suggested options for further channel length reduction to submicron dimensions.
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