Device Structure and Passivation Options for the Integration of Scaled IGZO TFTs

Abstract

The focus of this work is on the performance dependence of scaled IGZO TFTs with variations in gate electrode configuration and passivation options. A conservative process for the fabrication of long channel length devices (i.e. L ≥ 2 µm) exhibits long-channel behavior and excellent stability in both bottom-gate (BG) and double-gate (DG) configurations [1,2]. As the devices are scaled to shorter channel lengths, limitations of the device electrostatics begin to give way to short channel behavior. Dielectrics used for the gate and back-channel regions are typically adjusted to overcome short-channel effects as lateral dimensions are reduced. However certain interaction effects require additional process modifications for the desired device response and to accommodate the details of process integration. Scaled devices with channel lengths L < 2 µm are under investigation, with process conditions evaluated by quantitative measures on the materials properties, electrostatic behavior, and stability when subjected to bias and thermal stress. Process recipes for PECVD passivation layers, oxygen ambient annealing, and ALD capping materials are under reevaluation for their impact on short-channel devices. TCAD simulation is used as a resource to refine material and device models [3], and provide insight on the details which establish the limits of device operation. Design rule scaling and self-aligned gate device structures are also being studied for reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. [1] T. Mudgal, N. Edwards, P. Ganesh, A. Bharadwaj, Eli Powell, M.S. Pierce, R. G. Manley, and K. D. Hirschman, “Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability”, ECS Trans. 75 (10), 189-197 (2016) [2] M.S. Kabir, P. Ganesh, R.R. Chowdhury, H. Sethupathi, J. Okvath, J. Konowitch, R.G. Manley and K.D. Hirschman, “Channel-length dependent performance degradation of thermally stressed IGZO TFTs”, ECS Trans. 86 (11), 125-133 (2018) DOI: 10.1149/08611.0125ecst [3] K.D. Hirschman, T. Mudgal, E. Powell and R.G. Manley, “A 2D empirical model for on-state operation of scaled IGZO TFTs exemplifying the physical response of TCAD simulation”, ECS Trans. 86 (11), 153-166 (2018) DOI: 10.1149/08611.0153ecst Figure 1