Reconfigurable Field Effect Transistor Research Articles

Nonvolatile Reconfigurable Logic Device Based on Photoinduced Interfacial Charge Trapping in van der Waals Gap.

Due to the increasing complexity in miniaturization of electronic devices, reconfigurable field-effect transistors (RFETs) have emerged as a solution. Although the foundational concepts of RFETs have matured over two decades, ongoing breakthroughs are needed to address challenges such as improving the device performance as well as achieving balanced symmetry between n-type and p-type transport modes with long-term stability. Herein, we present a nonvolatile WSe2-based RFET that utilizes photoassisted interfacial charge trapping at the h-BN and SiO2 interface. Unlike typical RFETs with two gate electrodes, our RFETs achieved polarity control with a single operating gate activated exclusively under white-light exposure. The threshold voltage was tunable, ranging from 27.4 (-31.6 V) to 0.9 (+19.5 V), allowing selective activation of n-type (p-type) operation at VGS = 0 V. Additionally, our WSe2-based RFETs show superior repeatability and long-term stability. Leveraging these advantages, various reconfigurable logic circuits were successfully demonstrated, including complementary inverters and switch circuits as well as pull-up and pull-down circuits, highlighting the potential of WSe2 FETs for future advancements of integrated circuits.

A novel nanosheet reconfigurable field effect transistor with dual-doped source/drain

—In this paper, a reconfigurable field-effect transistor (RFET) with dual-doped nanosheet architecture and triple independent gates is proposed and studied with the numerical simulations. The proposed RFET can behave as either an n/p-type MOSFET or an n/p-type tunneling-FET (TFET) according to different program biases. A comprehensive study is carried out on the device mechanism and the influence of key device parameters. Various metrics, such as the on-state current (ION), off-state current (IOFF), ION/IOFF, threshold voltage (VT) and sub-threshold swing (SS), are used to evaluate the proposed RFET. This RFET combining the advantages of the conventional MOSFETs (High ION and operation speed) and the new emerging TFETs (Low IOFF, sub-threshold swing and power dissipation) could make the circuit design more flexible and high efficiency, and improve the circuit performance.

Novel Reconfigurable Field-Effect Transistor With Surrounded Source/Drain to Improve On-State Current

Novel Reconfigurable Field-Effect Transistor With Surrounded Source/Drain to Improve On-State Current

Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi‐Wire Channels

AbstractIn this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.

A paradigm shift in analog applications through reconfigurable FET

This paper presents the radio frequency (RF) and linearity analysis of a dual dielectric (DD) reconfigurable FET (RFET) for a wide variety of analog applications. A RFET can either act as a MOSFET or a TFET based on the electric potential applied externally over source and drain regions. The impact of DD reduces ambipolar current to large extent. Hence, DD-RFET is a multi functional (MF) device that can be configured in such a way that superior analog properties can be obtained at reduced static power loss. We found that DD-RFET processes a threshold voltage (Vth)= 0.2 V, transconductance (gm) = 4 mS, and gain bandwidth product (GBP) = 0.4 THz in nMOSFET configuration, while Vth = 0.64 V and subthreshold swing (SS) = 34 mV/decade in nTFET configuration. Also, DD-RFET has a Vth= 0.14 V, gm = 0.3 mS, and GBP = 17 GHz in pMOSFET configuration, while Vth = 0.52 V and SS = 31 mV/decade in pTFET configuration. Hence, DD-RFET eases circuit design as this MF device helps to provide high performance and low power using multi threshold (MT) technology. Also, we found that MOSFET has better linearity at low bias voltage and as the gain increases with the supply, promotes noise and distortion in the output. However, TFET produces more stable results at higher bias voltage than MOSFET. Hence, there is a clear trade-off in active power and linearity exist in RFET designs.

Novel Reconfigurable Field-Effect Transistor With Arch-Shaped Gate to Improve On-State Current

Novel Reconfigurable Field-Effect Transistor With Arch-Shaped Gate to Improve On-State Current

Design of Energy-Efficient RFET-Based Exact and Approximate 4:2 Compressors and Multipliers

The ever-increasing demand for low-power and area-efficient circuits for use in battery-powered devices and the CMOS scaling problems have attracted the attention of VLSI designers to beyond-CMOS technologies like Reconfigurable Field-Effect Transistors (RFETs). Improving the efficiency of multipliers is critical as the core component of many applications such as image processing and Machine Learning (ML). This paper proposes a compact and energy-efficient RFET-based architecture for the 4:2 compressor and Dadda multiplier, leveraging transistor-level reconfigurability and multi-input support of the RFET. Moreover, we propose a novel approximate 4:2 compressor based on efficient RFET logic cells to cater to the needs of error-resilient applications. Extensive circuit-level simulations with 14nm germanium nanowire (GeNW) RFET technology show that the proposed RFET-based exact multiplier improves the power consumption and power-delay product (PDP) by 65% and 45%, respectively, compared to the conventional CMOS-based counterpart in 14nm FinFET technology. Besides, we show that utilizing the proposed approximate compressor, the area and PDP of the multiplier reduce by 46% and 42%. The effectiveness of the approximate multiplier is evaluated in the image multiplication, and the average PSNR and SSIM values are 31.39 and 0.87, respectively.

Improved RFET Performance Using Dual-Aluminum-Contact (DAC)

The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this work.Many conventional RFETs contain NiSi source/drain (S/D) contacts, or other contacts with mid-gap S/D material, providing a symmetrical current between holes and electrons. However such contacts decrease injection of current [5 - 7]. Devices based on dual-doping (DD), provided a significant improvement in the current level, in addition to the ease fabrication due to the absence of the silicidation process, such technology cannot act in doping-free CMOS processes [6] [8]. Figure 2 shows the drain current as a function of the control gate voltage (IDS -VCG) for the BESOI MOSFET.This work presents a new proposal for a dual-contact S/D (DC) RFET, without the presence of DD regions and doping process, enabling dopants-free CMOS processes, using only S/D aluminum contacts, performed through Sentaurus TCAD simulations [9].Recently in the Integrable Systems Laboratory of the University of São Paulo (LSI-USP), two RFET with aluminum S/D contacts were reported. Both presented a high current for only one type of carrier (holes or electrons) [10 - 13]. The BESOI MOSFET conducts current through its back interface, where the channel between S/D contacts is formed by the bias of the programming gate (VPG), thus its operating mode is divided into P-type (VPG < 0 ) and N-type (VPG > 0). The transistor drain current is controlled by control gate voltage (VCG) [5] [10 - 11].The Figure 3 shows the drain current balanced as a function of the control gate voltage (ID -VCG), for aluminum BESOI MOSFET’s with and without annealing process (W/A, Wo/A) after the metal deposition [10 - 11]. Using both BE SOI MOSFET with S/D aluminum contact, without process doping, a new RFET Dual Aluminum Contact (DAC) is shown Figure 4.The challenge the design is to flow of current (holes) through the outer contact (W/A contact), due to the influence of the inner schottky low-barrier aluminum contact (Wo/A contact) near to the back interface. Figure 5 shows the carrier density as a function of the depth of the silicon under the inner contact, for different silicon thicknesses (tSi) and fixed programming gate voltage (VPG). The high concentration of electrons near to the inner contact, provided an ohmic contact for electrons [11], however near the back interface, an increasing concentration of holes, due to VPG. Increasing the tSi reduces the influence of charges near the back interface, for tSi=30nm the current flow between the outer contact is possible. However, increasing the tSi decreases the efficiency of the control gate, added to the high electric field in back interface increases IOFF (similar effect described for FD SOI [14]). The Figure 6 shows the drain current as a function of the control gate voltage of BESOI nMOSFET with tSi = 30nm. Such effect can be mitigated, optimizing the coupling the gates. Figure 7 shows the final proposal of the BESOI MOSFET DAC.Figure 8 shows the IDS-VCG for different thicknesses in the S/D contacts (tsi cont). As shown in Figure 5, a greater thickness in the contacts makes possible a smaller influence of the inner contact near the back interface, allowing greater concentrations of gaps, so consequently there is an increase in the p-mode current. However, increasing the thickness of the contacts promotes a reduction in the electron current, due to the increase in the series resistance in inner contact in n-mode.Figure 9 presents the ID-VCG for different VPG bias for the DAC BESOI MOSFET (A) and NiSi BESOI MOSFET (B). Using the DAC BESOI MOSFET, an increase in current was obtained in relation to the NiSi contact (900% in n-type and 300% in p-type), without the addition of doping regions (dual-doping) and using a single contact metal (Aluminum). Figure 1

A highly integrated nonvolatile bidirectional RFET with low leakage current

A highly integrated nonvolatile bidirectional reconfigurable FET controlled by a single gate (SGCN-BRFET) is proposed. The nonvolatile function, the bidirectional function and the reconfigurable function can be achieved at the same time. Instead of the independently powered program gate (PG) of BRFET, the program operation of the proposed SGCN-BRFET can be independently completed by the control gate (CG) itself through storing positive or negative charges in a floating program gate (FPG) formed on both source/drain sides. Thereafter, the interconnection can be simplified. The conduction type of the SGCN-BRFET is reconfigured by programming the FPG with different type of charges into the FPG. By optimizing the quantities of the stored charges, the FPG effective voltage can be changed to achieve higher forward current and lower leakage current. The physical mechanism of the proposed SGCN-RFET has been systematically analyzed. The device performance has been compared with BRFET. The influence of the amount of charge to the device performance has also been discussed in detail.

Novel Mixed-Dimensional hBN-Passivated Silicon Nanowire Reconfigurable Field Effect Transistors: Fabrication and Characterization.

This work demonstrates the novel concept of a mixed-dimensional reconfigurable field effect transistor (RFET) by combining a one-dimensional (1D) channel material such as a silicon (Si) nanowire with a two-dimensional (2D) material as a gate dielectric. An RFET is an innovative device that can be dynamically programmed to perform as either an n- or p-FET by applying appropriate gate potentials. In this work, an insulating 2D material, hexagonal boron nitride (hBN), is introduced as a gate dielectric and encapsulation layer around the nanowire in place of a thermally grown or atomic-layer-deposited oxide. hBN flake was mechanically exfoliated and transferred onto a silicon nanowire-based RFET device using the dry viscoelastic stamping transfer technique. The thickness of the hBN flakes was investigated by atomic force microscopy and transmission electron microscopy. The ambipolar transfer characteristics of the Si-hBN RFETs with different gating architectures showed a significant improvement in the device's electrical parameters due to the encapsulation and passivation of the nanowire with the hBN flake. Both n- and p-type characteristics measured through the top gate exhibited a reduction of hysteresis by 10-20 V and an increase in the on-off ratio (ION/IOFF) by 1 order of magnitude (up to 108) compared to the values measured for unpassivated nanowire. Specifically, the hBN encapsulation provided improved electrostatic top gate coupling, which is reflected in the enhanced subthreshold swing values of the devices. For a single nanowire, an improvement up to 0.97 and 0.5 V/dec in the n- and p-conduction, respectively, is observed. Due to their dynamic switching and polarity control, RFETs boast great potential in reducing the device count, lowering power consumption, and playing a crucial role in advanced electronic circuitry. The concept of mixed-dimensional RFET could further strengthen its functionality, opening up new pathways for future electronics.

Triboelectric-potential configurable MoTe2 homojunction for photovoltaic device and logic circuits

Reconfigurable devices based on two-dimensional materials are considered as one of the ways to extend Moore's Law. However, most reconfigurable devices use a gate voltage to dope the channel electrostatically, and the continuously applied gate voltage poses the problem of high device power consumption. Here, for the first time, we propose a tribotronic reconfigurable MoTe2 field effect transistor, where the power consumption of the device is greatly reduced by using triboelectric potentials generated by external mechanical operations instead of applying gate voltages. The drain current noise spectral density test proves that no additional current noise interferes with the output current during mechanical operation. Mechanical operation allows facile modulation of four different channel polarities (n-n, p-p, p-n, and n-p) in a single transistor. We demonstrate the potential application of a tribotronic p-n diode for photovoltaic device. The logic circuit composed of two tribotronic reconfigurable transistors realizes the logic functions of inverter, AND gate, and OR gate. Our device extends tribotronic logic and demonstrates great potential for human-machine interaction, intelligent sensors, and wearable devices.

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate.

A complementary doped source-based reconfigurable Schottky diode (CDS-RSD) is proposed for the first time. Unlike other types of reconfigurable devices that have source and drain (S/D) regions with the same material, this has a complementary doped source region as well as a metal silicide drain region. Compared to three-terminal reconfigurable transistors, which have both the program gate and control gate, the proposed CDS-RSD does not have a control gate but only a program gate for reconfiguration operation. The drain electrode of the CDS-RSD is not only the output terminal of the current signal but also the input terminal of the voltage signal. Therefore, it is a reconfigurable diode based on high Schottky barriers for both the conduction band and valence band of silicon, which formed on the interface between the silicon and drain electrode. Therefore, the CDS-RSD can be regarded as the simplification of the reconfigurable field effect transistor structure on the premise of retaining the reconfigurable function. The simplified CDS-RSD is more suitable for the improvement of logic gate circuit integration. A brief manufacture process is also proposed. The device performance has been verified through device simulation. The performance of the CDS-RSD as a single-device two-input equivalence logic gate has also been investigated.

Cross-shape reconfigurable field effect transistor for flexible signal routing

Cross-shape reconfigurable field effect transistor for flexible signal routing

A nonvolatile bidirectional reconfigurable FET based on S/D self programmable floating gates.

A nanoscale nonvolatile bidirectional reconfigurable field effect transistor (NBRFET) based on source /drain (S/D) self programmable floating gates is proposed. Comparing to the conventional reconfigurable field effect transistor (RFET) which requires two independently powered gates, the proposed NBRFET requires only one control gate. Beside, S/D floating gates are introduced. Reconfigurable function is realized by programming different types of charges into the S/D floating gates through biasing the gate at a positive or negative high voltage. The effective voltages of the S/D floating gates are determined jointly by the quantity of the charge stored in the S/D floating gates and the gate voltage. In addition, the charge stored in the floating gate has an effect of reducing the energy band bending near the source/drain regions when the gate is reversely biased, thereafter, the band to band tunneling (BTBT) leakage current can be largely decreased. The scale of the proposed NBRFET can be reduced to nanometer level. The device performances such as the transfer and output characteristics are verified by device simulation, which proves that the proposed NBRFET has very good performance in the nanometer scale.

Improved RFET Performance Using Dual-Aluminum-Contact (DAC)

This work presents for the first time the use of dual aluminum contacts (DAC) to improve the performance of reconfigurable field effect transistors (RFET), integrating two aluminum contact in BESOI MOSFET (with and without annealing process). Using TCAD simulations, the charge density in the channel region below the aluminum source contact depends on the channel thickness and bias in the programming gate. This thickness making possible to create a hole’s channel below the Schottky aluminum contact for silicon thickness below the aluminum contacts higher than 30nm, enabling conduction in the dual aluminum contact transistor. The DAC BESOI MOSFET had a current level increase of 3 times for BESOI pMOSFET and 9 times in BESOI nMOSFET compared to using NiSi contacts

A dual doping nonvolatile reconfigurable FET

In this work, we propose a dual doping based nonvolatile reconfigurable field effect transistor with source/drain (S/D) charge storage layers (DDN R-FET). It introduces nonvolatile charge storage layers on both source and drain sides as a floating program gate (FPG) instead of a program gate (PG) that needs independent power supply. The stored charges in the FPG are programmed by the control gate (CG). Therefore, the proposed DDN R-FET essentially requires only one independently powered gate to complete the reconfigurable operation. Moreover, by adjusting the charge stored in the FPGs, the CG can regulate the equivalent voltage in the FPG, which can promote the on-state current and reduce the generation of reversely biased leakage current at the same time. The physical mechanism has also been analyzed in details.

A complementary low-Schottky-barrier S/D-based nanoscale dopingless bidirectional reconfigurable field effect transistor with an improved forward current

In this paper, a nanoscale dopingless bidirectional RFET (BRFET) is proposed. Unlike conventional BRFETs, the proposed BRFET uses two different metal materials to form two different types of Schottky barriers on the interface between the S/D and silicon. For one of the two metal forms, the Schottky barrier height between the conduction band of the semiconductor and one of the two metal materials is lower than half of the energy band gap. The Schottky barrier height between the valence band of the semiconductor and the other kind of the two metal materials is lower than half of the energy band gap of the semiconductor. Therefore, a complementary low Schottky barrier (CLSB) is formed. Therefore, more carriers from the source electrode can easily flow into the semiconductor region through thermionic emission in both n-mode and p-mode compared to conventional BRFET operation, which generates carriers through the band-to-band tunneling effect. Therefore, a larger forward current can be achieved by the proposed CLSB-BRFET. The performance of the CLSB-BRFET is investigated by device simulation and compared with that of the BRFET. The working principle is interpreted through an analysis based on energy band theory. The output characteristics and reconfigurable function are also investigated and verified.

A Novel Single Gate Controlled Nonvolatile Floating Program Gate Reconfigurable FET

AbstractIn this work, a single gate controlled nonvolatile floating program gate (FPG) reconfigurable field effect transistor (RFET) is proposed. Different from the traditional RFET, it introduces a nonvolatile charge storage layer as an FPG instead of a program gate that needs independent power supply. The stored charge in the FPG can be programmed by the control gate (CG). Therefore, the proposed FPG‐RFET essentially requires only one independently powered gate to complete the reconfigurable operation. Moreover, the CG can regulate the equivalent voltage in the FPG, which can effectively reduce the static power consumption and the generation of reverse leakage current. The physical mechanism has also been analyzed in detail.

Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors [referred to as reconfigurable field-effect transistors (RFETs)] enable dynamic reconfiguration to demonstrate either a p- or an n-type functionality. This duality of functionality at the transistor level is efficiently abstracted as a self-dual Boolean logic, that can be physically realized with fewer RFET transistors compared to the contemporary CMOS technology. Consequently, to achieve better area reduction for RFET-based circuits, the self-duality of a given circuit should be preserved during logic optimization and technology mapping. In this article, we specifically aim to preserve self-duality by using Xor-majority graphs (XMGs) as the logic representation during logic synthesis and technology mapping. We propose a synthesis flow that uses new restructuring techniques, called rewriting and resubstitution for XMGs to preserve self-duality during technology-independent logic synthesis. For technology mapping, we use a novel open-source and a logic-representation agnostic mapping tool. Using the above-proposed XMG-based flow, we demonstrate its benefits by comparing post-mapping areas for synthetic and cryptographic benchmarks with three different synthesis flows: 1) AIG-based optimization and AIG-based mapping; 2) XMG-based optimization with AIG-based mapping; and 3) AIG-based optimization with logic-representation agnostic mapping. Our experiments show that the proposed XMG-based flow efficiently preserves self-duality and achieves the best area results for RFET-based circuits (up to 12.36% area reduction) with respect to the baseline.

Low Thermal Budget Reconfigurable Fully Depleted Silicon on Insulator Field-Effect-Transistors With Embedded Boolean Logic

We report the low thermal budget reconfigurable fully depleted silicon on insulator (FDSOI) field-effect-transistors, focusing on the management of the fabrication thermal budget, toward three-dimensional integration and the further improvement of the circuit functionality. This is realized using atomic layer deposition tool-enabled O2/NH3 plasma surface passivation technology and long duration thermal procedure. Moreover, such front-gated FDSOI reconfigurable field effect transistors (RFETs) gain the embedded Boolean logic of “AND” and “NOR” in N and P-type modes, respectively. This strategy has the potential to be a key enabler for functional improvement in the nanoscale hyper-scaling era.