Reconfigurable Field Effect Transistor Research Articles

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits

Emerging nanotechnologies based reconfigurable field-effect transistors (RFETs) allow switching between p-type and n-type behavior at runtime upon application of different bias potentials. While prior works have mainly focused on security schemes using RFETs, here we revisit the underlying security promises, and furthermore, showcase certain circuit vulnerabilities which can lead to adversarial scenarios. More specifically, first, we explore how transistor-level reconfigurability can be leveraged for logic locking and split manufacturing in the pretext of RFET-based modeling of the ITC-99 circuits. We find that with only 30% reconfigurable logic gates, we can induce 100% output error rate (OER) and 31% Hamming distance(HD) on split-manufacturing schemes. Second, which is arguably more disruptive, we explore how the very reconfigurability can be exploited to induce either short-circuit or open-circuit configurations, essentially destroying the reliability, electrical, or functional characteristics of the chip. By means of fault modeling for such exploitation, 100% OER (across all benchmarks) as well as 36.5%, 40.02%, and 6.34% HD, respectively, can be expected for the MCNC, EPFL, and ITC-99 benchmarks. The novelty and severity of such disruptive scenario lies in the fact that they can be readily realized in an actual on-field RFET-based chip, either as an adversarial or a fail-safe measure.

Investigation on Temperature Dependency of Recessed-Channel Reconfigurable Field-Effect Transistor

Current-voltage (I-V) characteristics of a recessed-channel reconfigurable field-effect transistor (RC-RFET) is discussed, herein, depending on the variation of temperature (T) to understand the operation mechanisms, in depth. Assuming that RC-RFET can be simply modeled as a channel resistance (RCH) and a Schottky contact resistance (RSC) connected in series, the validity has been examined by a technology computer-aided design (TCAD) simulation with different Schottky barrier heights (SBHs) and carrier mobilities (μ). As a result, it was clearly determined that the drain current (ID) of RC-RFET is dominated by the bigger component, since RCH and RSC have an opposite correlation with T.

Nanowire reconfigurable FET as biosensor: Based on dielectric modulation approach

In this paper, we have developed analytical surface potential and threshold voltage model of nanowire reconfigurable Field Effect Transistor (FET) which acts as a biosensor to detect the biomolecules, based on dielectric modulation approach. Due to its reconfigurable behavior, it acts as both p-type and n-type depending on the polarity of the biasing and hence find wide spread applications in the field of Programmable Logic Arrays (PLAs). The same is employed here as a bio sensor device with split gates and a cavity for biomolecules immobilization on a thin layer of silicon dioxide as adhesive layer. When the biosensor interacts with the bio targets of the cavity, the electrostatic properties of the device including variation in potential profile and threshold voltage shift get affected and thus have been identified as detection metric in this present work. The characteristic trends of the biosensor are studied with varying height, dielectric constant and charge of the bio-species as polarity of the applied biases change. In addition to this, sensitivity of nanowire RFET is analyzed by assessing the threshold voltage variation which is further compared with equivalent MOSFET biosensor. All the analytical results obtained are corroborated with technology computer-aided-design (TCAD) simulation data to verify the precision of our model.

Towards Reconfigurable Electronics: Silicidation of Top-Down Fabricated Silicon Nanowires

We present results of our investigations on nickel silicidation of top-down fabricated silicon nanowires (SiNWs). Control over the silicidation process is important for the application of SiNWs in reconfigurable field-effect transistors. Silicidation is performed using a rapid thermal annealing process on the SiNWs fabricated by electron beam lithography and inductively-coupled plasma etching. The effects of variations in crystallographic orientations of SiNWs and different NW designs on the silicidation process are studied. Scanning electron microscopy and transmission electron microscopy are performed to study Ni diffusion, silicide phases, and silicide–silicon interfaces. Control over the silicide phase is achieved together with atomically sharp silicide–silicon interfaces. We find that {111} interfaces are predominantly formed, which are energetically most favorable according to density functional theory calculations. However, control over the silicide length remains a challenge.

Electron transport through NiSi2–Si contacts and their role in reconfigurable field-effect transistors

A model is presented which describes reconfigurable field-effect transistors (RFETs) with metal contacts, whose switching is controlled by manipulating the Schottky barriers at the contacts. The proposed modeling approach is able to bridge the gap between quantum effects on the atomic scale and the transistor switching. We apply the model to transistors with a silicon channel and NiSi2 contacts. All relevant crystal orientations are compared, focusing on the differences between electron and hole current, which can be as large as four orders of magnitude. Best symmetry is found for the orientation, which makes this orientation most advantageous for RFETs. The observed differences are analyzed in terms of the Schottky barrier height at the interface. Our study indicates that the precise orientation of the interface relative to a given transport direction, perpendicular or tilted, is an important technology parameter, which has been underestimated during the previous development of RFETs. Most of the conclusions regarding the studied metal-semiconductor interface are also valid for other device architectures.

An analytical model for a reconfigurable tunnel field effect transistor

In this work, an analytical model for surface potential and current through a reconfigurable tunnel field effect transistor (RTFET) are proposed. While obtaining the mathematical potential model, the whole channel region is divided into three: two regions with gate electrodes and a region in between two gates. The 2D Poisson′s equation is solved in the region under the gate by appropriately selecting the boundary conditions. The current model is derived by integrating the band to band generation rate. The analytical models are validated using technology computer-aided design (TCAD) simulation and the analytical model and TCAD simulations are in good agreement.

Reconfigurable Field-Effect Transistor as a Synaptic Device for XNOR Binary Neural Network

A reconfigurable field-effect transistor (RFET) with memory functionality is proposed as a new high-density synaptic device capable of exclusive NOR (XNOR) operation for a binary neural network (BNN). A RFET with three gates is used in this letter, consisting of two program gates (PGs) electrically connected to each other and a control gate (CG) between the PGs. By changing the polarity of the PG bias or the polarity of the charge trapped in Si3N4 layer on the PGs, the RFET operates as an ${n}$ - or a ${p}$ -MOSFET having a CG as a switching gate. The XNOR operation is successfully demonstrated in a fabricated RFET. The on/off current ratio (the ratio of 1 to 0 in the result of the XNOR operation) is ~104 and the current is ~1 nA/ $\mu \text{m}$ . Using a RFET as a synaptic device for a BNN is efficient in terms of the area (~8F2/synapse) because XNOR operation can be performed using only one RFET.

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.

U-shaped Reconfigurable Field-effect Transistor

We propose a novel reconfigurable fieldeffect transistor (RFET) featuring two verticallystacked gates and a U-shaped nanowire channel. Conventional RFETs have a relatively large unit cell size due to their configuration with multiple gates. However, the proposed device can solve this inherent disadvantage of RFET. In addition, it can have a long enough channel without additional area, so that excellent characteristics can be obtained without the short channel effects. The characteristics of the proposed device were examined by 3-D technology computer-aided design (TCAD) device simulation. The effect of some device parameters on the device performance were investigated. Also, the fabrication method is proposed.

Vertically Integrated Reconfigurable Nanowire Arrays

This letter discusses a feasible variant of vertically integrated reconfigurable field effect transistors (RFET) based on top–down nanowires. The structures were studied by 3-D device simulations. Subdividing the structure into two vertical pillars allows a lean technological realization as well as simple access to the electrodes. In addition of enabling p- and n-FET operations like a horizontal RFET, the device delivers higher performance. We show that by the integration of additional vertical pillars and select gates, a higher device functionality and flexibility in interconnection are provided.

A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET

In this paper, we have developed a physics-based compact model for surface potential and drain current for a dual gate source/drain (S/D) spacer-based silicon nanowire reconfigurable field-effect transistor (RFET). The models are derived by dividing the active region of the device into several portions based on positioning of the gates, spacers, and the metal-silicide Schottky junctions. A charge density expression is first developed and the quasi-fermi potentials for both electron and hole transport are found out by applying the principle of current continuity. Using these and further solving the 2-D Poisson’s equation self consistently for various subregions of the device, the drain current and surface potential are modeled subsequently. The model includes the effects of drain voltage, nanowire radius, temperature and Schottky barrier height. The accuracy of the derived results is tested using 3-D numerical technology computer aided design simulations. The proposed model can be used to study the behavior of ambipolar FETs having S/D spacers for varying device dimensions and also can be utilized for the future design of memory devices and circuits using spacer-based RFETS.

Two dimensional analytical model for a reconfigurable field effect transistor

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-to-band tunneling (BTBT) for their on-current generation. It is observed that the output characteristics of the device are less sensitive to the temperature in the BTBT dominated on-state region as compared to the subthreshold one which is thermionic emission dependent. Having a better thermal stability over tunnel field effect transistor (TFET) and significantly lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-all-around (GAA) and hetero gate dielectric GAA TFET devices over the considered range of temperature, thus assuring higher switching speed for digital applications. Moreover, superior analog/RF performance is also exhibited by the device under consideration for all temperatures in contrast to SiGe, full silicon TFETs, and conventional RFET topology owing to higher BTBT dominance and better gate controllability. Apart from all of these performance gains, the device FOMs are found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern.

Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

In this paper, a technology for top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such silicon-on-insulator-based devices. The symmetry in the current-voltage-characteristics is a mandatory requirement to realize circuits with reconfigurable nanowire field effect transistors (RFETs) whose channel can be switched electrostatically between n- and p-conductance. It was achieved by an oxidation-induced stressor layer covering the nanowire. Together with the demand for only a single gate potential level, this opens the route to build top-down RFET circuits. Our device features an atomically sharp Schottky junction between intruded nickel silicide and the intrinsic nanowire channel.

Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET

A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of varying the gate–channel and spacer-channel underlap on the device characteristics of such a DG-RFET is reported for the first time in this paper. It is demonstrated that by appropriate designing of the gate- and spacer-channel underlap, the on-current and on–off current ratio of the device can be significantly improved. Moreover, it is also found that increasing the gate dielectric constant for a fixed equivalent oxide thickness improves its delay performance. Finally, we have also reported results related to the scaling properties of such a device.

Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations

Reconfigurable FETs (RFETs) are optimized in planar Fully Depleted (FD) SOI. Their basics, electrostatics and performance are studied and compared with standard 28nm FDSOI and other RFETs results in the literature. The main challenge for future broad adoption is analyzed and commented. Finally, some tips to improve the performance such as the asymmetric silicidation at source/drain are discussed.

(Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits

Semiconductor nanowire transistors are considered potential successors of finFETs providing the ultimate miniaturization capabilities of MOS transistors and thus targeting ultimate circuit complexity and performance. A promising perspective for further advancement beyond classical CMOS scaling is to exploit functionality enhancement of nanowire transistors. Several nanowire based multi-gated device concepts known as reconfigurable field effect transistors (RFETs) or polarity control FETs that combine multi-functionality with the inherent advantages of silicon nanowires are being currently evaluated [1-4]. These multi-terminal devices merge unipolar n- and p- FET switching characteristics from the same device as selected simply by an electric signal and without the need for doping enabling complementary CMOS operation with a single kind of transistor. RFETs make use of two sharp metal-NiSi2 / intrinsic-silicon interfaces with individual gates for the selective injection of electrons and holes into the channel region [5]. Additional independent steering gates can be integrated to further enhance functionality without comprising on-conductance [6]. In order to allow complementary circuit operation symmetry in the p- and n-type I-Vcharacteristics is mandatory. To this end, we show both experimentally [7] and by device simulations [8] that the application of radial compressive strain to <110> oriented silicon nanowires is able to align the injection efficiency of electrons and holes for diverse nanowire geometries. Full swing complementary operating circuits such as inverters [7] and compact six transistor cells yielding NAND, NOR and minority functions as demonstrated with symmetric RFETs and 3XOR gates with only 8 transistors vs. 24 with CMOS [6,7,10,11]. These gates build the basis for arithmetic building blocks such as one-bit adders with substantially lower transistor count reducing critical pathes, delay and power consumption as compared to conventional CMOS [6]. The RFET concept has been recently successfully transferred to a parallel nanowire technology [12,13] principally enabling to build low operation power circuits and sensors on plastic substrates. Finally, we show that germanium based RFETs improve the individual device performance and to reduce dynamic power consumption without comprising static power consumption. Figure caption: a) Schematic of reconfigurable nanowire FET (RFET) encompassing intrinsic Si nanowire channel and two independently gated Si / NiSi2 junctions. b) Oxide induced compressive stress in Si nanowire core required to adjust electron and hole currents: TEM cross section of nanowire channel with overlay of computed mechanical strain distribution. c) SEM image of abrupt Si / NiSi2 junction. d) SEM of symmetrically operating RFET with electrical device symbol. e) Symmetric p- and n-program I-V transfer characteristics of device depicted in d). f) SEM of inverter built of two RFETs within a single nanowire. g) Measured inverter transfer characteristic with supply voltage of Vdd = 2V showing low operation power complementary behavior and full swing output. Propagation delay for scaled structure and for different fanouts. Output of reconfigrable NAND/NOR/Minority 6-transistor cell, shows reconfiguration at runtime (mixed -mode computations). h) High-yield printed silicon nanowire FETs encompassing ~ 1xE3 parallel nanowires with meander source/ drain / gate structure. Technology is compatible with flexible plastic substrates.

Recessed‐channel reconfigurable field‐effect transistor

A new reconfigurable field-effect transistor (RFET) named as recessed-channel RFET (RC-RFET) is introduced herein to improve scalability, current drivability and subthreshold swing (S). There are two distinct features which allow RC-RFET to show enhanced performance than conventional RFET. First, a novel structure based RC and stacked gates increases effective channel length which results in suppressed short-channel-effect without any integration density penalty. Second, the switching mechanism of RC-RFET (thermionic emission) differs from that of conventional RFET (Schottky barrier tunnelling). It enables RC-RFET to overcome the fundamental limit of S degradation as a function of gate voltage and promises higher ON–OFF current ratio (I ON/I OFF) and its low-power applications. As a result, the RC-RFET shows I ON/I OFF higher than 107, small drain induced barrier lowering about 15 mV/V and ideal S (∼63 mV/decade) for 50 nm gate length.

High-Performance Reconfigurable Si Nanowire Field-Effect Transistor Based on Simplified Device Design

Reconfigurable field-effect transistors (RFETs) are of interest as devices for dynamically switching between n- and p-type polarity which enables different logic computations using the same hardware. So far, RFETs have been realized with one or even two additional program gates for accomplishing reconfigurability. This paper presents an RFET design with just one single-gate on a silicon nanowire channel. Based on measured and device simulation data of a double-gate (DG) RFET, it is shown that the proposed simplified single-gate (SG) RFET achieves the same functionality and dc characteristics as the more complex DG-RFET. Besides reducing the wiring for the program gate(s), the SG-RFET has the additional advantage of being scalable to smaller channel length and thus achieving higher operating speed.

Optimization of Design Parameters in Dual-k Spacer-Based Nanoscale Reconfigurable FET for Improved Performance

This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high- $\kappa $ source–drain ( $S/D$ ) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer ( $\vphantom {\sum _{R_{R_{r}}}} L_{\textrm {sp}}$ ), gate dielectric and its thickness ( $t_{\textrm {ox}}$ ) and intergate distance ( $d_{G1G2}$ ) on vital performance parameters of the device, such as $I_{\mathrm{\scriptscriptstyle ON}}$ , $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ , Subthreshold swing ( $S/S$ ), $V_{t}$ , and $g_{m}/I_{d}$ , is investigated and analyzed. It is observed that increasing the spacer length increases Band to band tunneling rate probability through the thin barriers at ON-state. Moreover, the permittivity of spacer material is found to be closely related to the lateral fringe lines emanated from gate, resulting in a boosted $I_{\mathrm{\scriptscriptstyle ON}}$ as well as $g_{m}/I_{d}$ at higher $\kappa _{\textrm {sp}}$ . Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON–OFF current ratio though $S/S$ remains mostly unaffected. However, intergate distance scaling is found to have a strong influence on device performance providing higher current drive and lower $S/S$ for both n- and p-programs at lower $d_{G1G2}$ .