Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET

Abstract

A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of varying the gate–channel and spacer-channel underlap on the device characteristics of such a DG-RFET is reported for the first time in this paper. It is demonstrated that by appropriate designing of the gate- and spacer-channel underlap, the on-current and on–off current ratio of the device can be significantly improved. Moreover, it is also found that increasing the gate dielectric constant for a fixed equivalent oxide thickness improves its delay performance. Finally, we have also reported results related to the scaling properties of such a device.