A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET

Abstract

In this paper, we have developed a physics-based compact model for surface potential and drain current for a dual gate source/drain (S/D) spacer-based silicon nanowire reconfigurable field-effect transistor (RFET). The models are derived by dividing the active region of the device into several portions based on positioning of the gates, spacers, and the metal-silicide Schottky junctions. A charge density expression is first developed and the quasi-fermi potentials for both electron and hole transport are found out by applying the principle of current continuity. Using these and further solving the 2-D Poisson’s equation self consistently for various subregions of the device, the drain current and surface potential are modeled subsequently. The model includes the effects of drain voltage, nanowire radius, temperature and Schottky barrier height. The accuracy of the derived results is tested using 3-D numerical technology computer aided design simulations. The proposed model can be used to study the behavior of ambipolar FETs having S/D spacers for varying device dimensions and also can be utilized for the future design of memory devices and circuits using spacer-based RFETS.