Readout Architecture Research Articles

Radiation hard monolithic CMOS sensors with small electrodes for High Luminosity LHC

The upgrade of the tracking detectors for the High Luminosity-LHC (HL-LHC) requires the development of novel radiation hard silicon sensors. The development of Depleted Monolithic Active Pixel Sensors targets the replacement of hybrid pixel detectors with radiation hard monolithic CMOS sensors. We designed, manufactured and tested radiation hard monolithic CMOS sensors in the TowerJazz 180 nm CMOS imaging technology with small electrodes pixel designs. These designs can achieve pixel pitches well below current hybrid pixel sensors (typically 50 × 50μm) for improved spatial resolution. Monolithic sensors in our design allow to reduce multiple scattering by thinning to a total silicon thickness of only 50μm. Furthermore monolithic CMOS sensors can substantially reduce detector costs. These well-known advantages of CMOS sensor for performance and costs can only be exploited in pp-collisions at HL-LHC if the DMAPS sensors are designed to be radiation hard, capable of high hit rates and have a fast signal response to satisfy the 25 ns bunch crossing structure of LHC. Through the development of the MALTA and Mini-MALTA sensors we show the necessary steps to achieve radiation hardness at 1015 neq/cm2 for DMAPS with small electrode designs. The sensors combine high granularity (pitch 36.4x36.4μm2), low detector capacitance (<5fF/pixel) of the charge collection electrode (3μm), low noise (ENC≈10 e−) and low power operation (1μW/pixel) with a fast signal response (25 ns bunch crossing). The sensors feature arrays of 512 × 512 (MALTA) and 16 × 64 (Mini-MALTA) pixels. To cope with high hit rates expected at HL-LHC (>200 MHz/cm2) we have implemented a novel high-speed asynchronous readout architecture. The paper summarises the optimisation of the pixel design to achieve radiation hard pixel designs with full efficiency after irradiation at >98% after 1015 neq/cm2).

Readout Architecture Based on a Novel Photon-Counting and Energy Integrating Processing for X-Ray Imaging

In this article, a new readout architecture for X-ray imaging is proposed, which is based on the energy weighting function. This architecture utilizes a spectrometer and an energy weighting logic per pixel. Various weights can be realized inside a pixel by changing only the logic implementation, and energy weighted pixel values are calculated without external calculations. The proposed architecture was confirmed that its weighting function could be modified by fabricating two weighting functions in the form of two test large-scale integrated circuits (LSIs) with a 0.18- $\mu \text{m}$ complementary metal–oxide–semiconductor (CMOS) process. They were designed for a photon counting and an energy integrating imager with 80- $\mu \text{m}$ pitch pixels, and their abilities to deal with different fluxes were evaluated after obtaining each simulation result. Their sensitivity to single photons and their capability in measuring the energy information of X-ray photons has been demonstrated by measuring the spectra of radiation isotopes.

Development of a low-noise front-end ASIC for CdTe detectors

We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 μm CMOS technology (X-Fab XH035), consists of 64 readout channels and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9e−± 11.3e− (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons within the energy from 6.4 keV to 122.1 keV are detected. Based on the experimental results, we propose a new low-noise readout architecture making use of a slew-rate limited mode at the shaper followed by a peak detector circuit.

Study of CMOS strip sensor for future silicon tracker

Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments.CHESS (CMOS HV/HR Evaluation for Strip Sensor) sensor series have been developed as an alternative solution to the conventional silicon micro-strip detectors for the ATLAS inner tracker upgrade. The first prototype (named CHESS1) was to evaluate the diode geometry and the in-pixel analog electronics. Obtained test results were used to optimize the second prototype (named CHESS2). CHESS2 was implemented with a full digital readout architecture and realized as a full reticle sized monolithic sensor. In this paper, the basic characteristics of the CHESS2 prototype sensors and their performance in response to different input signals are presented.

DMAPS Monopix developments in large and small electrode designs

LF-Monopix1 and TJ-Monopix1 are depleted monolithic active pixel sensors (DMAPS) in 150nm LFoundry and 180nm TowerJazz CMOS technologies respectively. They are designed for usage in high-rate and high-radiation environments such as the ATLAS Inner Tracker at the High-Luminosity Large Hadron Collider (HL-LHC). Both chips are read out using a column-drain readout architecture. LF-Monopix1 follows a design with large charge collection electrode where readout electronics are placed inside. Generally, this offers a homogeneous electrical field in the sensor and short drift distances. TJ-Monopix1 employs a small charge collection electrode with readout electronics separated from the electrode and an additional n-type implant to achieve full depletion of the sensitive volume. This approach offers a low sensor capacitance and therefore low noise and is typically implemented with small pixel size. Both detectors have been characterized before and after irradiation using lab tests and particle beams.

Data acquisition system for Belle II electromagnetic calorimeter

Since 2018, the Belle II experiment has been running at KEK, at the SuperKEKB B-factory, with all detector subsystems taking data. One of the important detector systems is an electromagnetic calorimeter (ECL) that includes 8736 counters based on CsI(Tl) scintillation crystals. This report describes the data acquisition (DAQ) system that has been developed for ECL. Front-end electronics of ECL DAQ consist of several hundred highly configurable FPGA-controlled modules that utilize pipeline readout architecture and are able to handle a trigger rate up to 30 kHz. ECL front end electronics are initialized, configured and monitored by ECL DAQ software. The initialization library can work with several transport protocols, internally optimize requests to the electronics and perform caching of the configuration data. Configuration software manages and monitors more than 105 electronics parameters and updates them based on the calibrations. Continuous monitoring of ECL data quality is also implemented.

Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subsequent iterations, from prototypes to a large pixel matrix comprising a complete readout architecture suitable for LHC operation. Full CMOS electronics is embedded in large deep n-wells which at the same time serve as collection nodes (large electrode design). The devices have been intensively characterized before and after irradiation employing lab tests as well as particle beams. The devices can cope with particle rates seen by the innermost pixel detectors of the LHC pp-experiments or as seen by the outer pixel layers of the planned HL-LHC upgrade. They are radiation hard to particle fluences of at least 1015 neq/cm2 and total ionization doses of at least 50 Mrad.

Scalable implementation of a superconducting nanowire single-photon detector array with a superconducting digital signal processor.

A two-dimensional single-photon imaging system with high sensitivity and high time resolution is the ultimate camera and useful in a wide range of fields. A superconducting nanowire single-photon detector (SSPD or SNSPD) is one of the best candidates for realizing such an ultimate camera due to its high detection efficiency in a wide spectral range, low dark count rate without after-pulsing, and excellent time resolution. Here we propose a new readout scheme to realize a large-scale imaging array based on SSPD, where a row-column readout architecture is combined with a digital signal processor based on a single-flux-quantum (SFQ) circuit. A 16-pixel row-column readout SSPD array is fabricated and measured with an SFQ digital signal processor. We successfully acquired spatial information as encoded digital bit codes with the temporal information of the photon detection. The system timing jitter was measured as <80 ps for all 16 pixels even through the SFQ signal processor, indicating the potential for an imaging array with an extremely high time resolution.

Characterization of Aliased Noise in the Advanced ACTPol Receiver

Advanced ACTPol is the second generation polarization-sensitive upgrade to the $6\, \rm m$ aperture Atacama Cosmology Telescope (ACT), which increased detector count and frequency coverage compared to the previous ACTPol receiver. Advanced ACTPol utilizes a new two-stage time-division multiplexing readout architecture based on superconducting quantum interference devices (SQUIDs) to achieve a multiplexing factor as high as 64 (rows), fielding a 2,012 detector camera at 150/220 GHz and two 90/150 GHz cameras containing 1,716 detectors each. In a time domain system, aliasing introduces noise to the readout. In this work we present a figure of merit to measure this noise contribution and present measurements of the aliased noise fraction of the Advanced ACTPol receiver as deployed.

Design and Performance of the First BICEP Array Receiver

Branches of cosmic inflationary models, such as slow-roll inflation, predict a background of primordial gravitational waves that imprints a unique odd-parity B-mode pattern in the Cosmic Microwave Background (CMB) at amplitudes that are within experimental reach. The BICEP/Keck (BK) experiment targets this primordial signature, the amplitude of which is parameterized by the tensor-to-scalar ratio r, by observing the polarized microwave sky through the exceptionally clean and stable atmosphere at the South Pole. B-mode measurements require an instrument with exquisite sensitivity, tight control of systematics, and wide frequency coverage to disentangle the primordial signal from the Galactic foregrounds. BICEP Array represents the most recent stage of the BK program, and comprises four BICEP3-class receivers observing at 30/40, 95, 150 and 220/270 GHz. The 30/40 GHz receiver will be deployed at the South Pole during the 2019/2020 austral summer. After 3 full years of observations with 30,000+ detectors, BICEP Array will measure primordial gravitational waves to a precision $\sigma(r)$ between 0.002 and 0.004, depending on foreground complexity and the degree of lensing removal. In this paper we give an overview of the instrument, highlighting the design features in terms of cryogenics, magnetic shielding, detectors and readout architecture as well as reporting on the integration and tests that are ongoing with the first receiver at 30/40 GHz.

A Digital Readout IC for Microbolometer Imagers Offering Low Power and Improved Self-Heating Compensation

This paper presents a novel and power efficient readout architecture for uncooled microbolometers that offers adequate noise performance along with a circuit-based method for self-heating compensation. The proposed method employs an event-generation scheme and a time-mode readout chain to achieve dynamic mode of operation resulting in low power. The readout chain consists of a capacitive transimpedance amplifier (CTIA) based current-to-time converter followed by a two stage time-to-digital converter (TDC). The CTIA employs a novel integration scheme for time amplification along with a modified reset mechanism to achieve self-heating compensation. We also present a model to analyze the implications of time-mode readout on imager operation. An experimental readout chip, based on this approach, has been designed using a 130 nm bulk CMOS technology. The proposed architecture offers robust frontend processing and achieves a per channel power consumption of $66~\mu \text{W}$ , which is considerably lower than the most recently reported designs, while maintaining better than 10-mK readout noise equivalent temperature difference (NETD).

Ideal Quantum Nondemolition Readout of a Flux Qubit without Purcell Limitations

Dispersive coupling based on the Rabi model with large detuning is widely used for quantum nondemolition (QND) qubit readout in quantum computation. However, the measurement speed and fidelity are usually significantly limited by the Purcell effects, i.e.: Purcell decay, critical photon numbers, and qubit-dependent Kerr nonlinearity. To avoid these effects, we propose how to realize an ideal QND readout of a gradiometric flux qubit with a tunable gap via its non-perturbative dispersive coupling (NPDC) to a frequency-tunable measurement resonator. We show that this NPDC-based readout mechanism is free of dipole-field interactions, and that the qubit-QND measurement is not deteriorated by intracavity photons. Both qubit-readout speed and fidelity can \emph{avoid the Purcell limitations}. Moreover, NPDC can be conveniently turned on and off via an external control flux. We show how to extend this proposal to a multi-qubit architecture for a joint qubit readout.

Analysis and Optimization design of the column bus parasitic effects on large-array CMOS image sensor

This paper analyzes the impact of column bus parasitic parameters on the output noise and response speed of the pixel signal in large-array CMOS image sensor (CIS), and the optimized column bus design scheme has been obtained. By building the mathematical model of the column bus, the relationship between output noise, response speed and the size of the column bus is revealed, and the influence of the column bus size on the sensor is evaluated by system impact factor (SIF). In 110 ​nm CMOS process and a 12.45 ​cm ​(H) ​× ​12.45 ​cm ​(V) pixel array, the double-ended readout architecture is utilized for output noise and response time analysis. Average output noise (146 ​μV) and response time (6.35 ​μs) are attained at column bus width of 0.5 ​μm. The experimental results show that for a given pixel array, the increase of the column bus width will cause output noise reduction and a longer response time. In the chip design, the column bus size could be optimized according to the relationship between output noise, response speed and pixel array size given in the paper.

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 × 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in average of 120 MHz can be processed with readout time of 50 ns per pixel and of less than 500 ns per double column of pixels. The layout area is 25.68 × 1.13 mm2. The power density in trigger mode and in triggerless mode are estimated as 25 ∼ 30 mW/cm2 and 35 ∼ 45 mW/cm2 respectively.

A Low-Complexity Hybrid Readout Circuit for Lidar Receiver

This brief presents a low-complexity hybrid readout architecture that can extract both timing and amplitude information of the return pulse concurrently for a light detection and ranging radar (Lidar) receiver. To reconstruct the short return pulse, the core circuit of one sampling and storage array with an embedded time-to-digital converter (SSA-TDC) is proposed. Instead of relying on the conventional power-hungry high-speed ADC, it selectively samples the interested return pulse with high speed and stores the voltages for later quantization in the long idle interval. In the preceding stage of the SSA-TDC, the analog front-end circuit cascaded of a narrow-bandwidth transimpedance amplifier, a voltage amplifier, and an equalizer circuit is included. The prototype chip of the eight readout channels is designed and fabricated with the 0.18- $\mu \text{m}$ CMOS process. The active circuit occupies an area of $1200\,\,\mu \text{m}\,\,\times 2100\,\,\mu \text{m}$ , and the power consumption of one single channel is 45 mW with 3.3-V supply. The proposed SSA-TDC has achieved a dynamic error of 180 ps in the experimental study.

A Generic High Bandwidth Data Acquisition Card for Physics Experiments

In high energy physics and nuclear physics experiments, particularly the ones based on a particle accelerator, the data rate from the detector is usually in the order of terabytes per second. These high throughput data from detector front-end electronics (FEEs) need to be transmitted to the back-end computing farm for high-level event selection and building. A data acquisition (DAQ) system with the features of high density, scalable, and easily upgradeable is crucial to simplify the readout architecture of the whole experiment. This article will introduce the design of a generic high bandwidth PCIe card, which can be used as the important input-output card in a scalable DAQ system. It can factorize FEEs from data handling and reduce the amount of custom hardware in favor of scalable detector-independent commercial hardware and software. Besides the 48 channels of bidirectional high-speed fiber optical links with front ends, it also supports to synchronize with the experiment timing system and to fan-out the clock and trigger information with a fixed latency to the FEEs.

A Multi-Functional Physiological Hybrid-Sensing E-Skin Integrated Interface for Wearable IoT Applications.

This paper presents a flexible multi-functional physiological sensing system that provides multiple noise-immune readout architectures and hybrid-sensing capability with an analog pre-processing scheme. The proposed multi-functional system is designed to support five physiological detection methodologies of piezo-resistive, pyro-resistive, electro-metric, opto-metric and their hybrid, utilizing an in-house multi-functional e-skin device, in-house flexible electrodes and a LED-photodiode pair. For their functional verification, eight representative physiological detection capabilities were demonstrated using wearable device prototypes. Especially, the hybrid detection method includes an innovative continuous measurement of blood pressure (BP) while most previous wearable devices are not ready for it. Moreover, for effective implementation in the form of the wearable device, post-processing burden of the hybrid method was much reduced by integrating a proposed analog pre-processing scheme, where only simple counting process and calibration remain to estimate the BP. This multi-functional sensor readout circuits and their hybrid-sensing interface are fully integrated into a single readout integrated circuit (ROIC), which is designed to implement three readout paths: two electrometric readout paths and one impedometric readout path. For noise-immune detection of the e-skin sensor, a pseudo-differential front-end with a ripple reduction loop is proposed in the impedometric readout path, and also state-of-the-art body-oriented noise reduction techniques are adopted for the electrometric readout path. The ROIC is fabricated in a CMOS process and in-house e-skin devices and flexible electrodes are also fabricated.

Conflux—An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout

This article describes an independent, self-arbitrating asynchronous two-to-one multiplexor called Conflux. Conflux can be used to implement clockless and tokenless time-division multiplexing between two sources. This capability can then be used to create a clockless and tokenless aggregate data bus that can be used as a complete asynchronous readout architecture for a chip, a part of a chip, or an entire multichip system. Conflux utilizes a classic, four-phased asynchronous handshake on both of its input ports as well as on its output port. Asynchronous Request is bundled with Data to ensure consistent propagation delay. The Request is also implemented as a differential signal to account for propagation delay differences between logical ones and zeros. Arbitration between the two Conflux input streams is accomplished by three Set–Reset Latches. Finally, Conflux cells were used successfully to implement the readout architecture of the FCP130 prototype chip. Tests indicate single Conflux stage delays of 1.8 ns and a bandwidth of approximately 11 Gb/s in 130-nm CMOS.

The PreProcessor module for the ATLAS Tile Calorimeter at the HL-LHC

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). In 2026, the LHC will be upgraded to the High Luminosity LHC (HL-LHC) allowing it to deliver up to 7 times the nominal instantaneous design luminosity. The Phase-II TileCal Upgrade will accommodate the detector and data acquisition system to the HL-LHC requirements. The on- and off-detector electronics will be completely redesigned using a new readout architecture with a full-digital trigger system. The upgraded on-detector electronics will transfer digitized data for every bunch crossing (∼25 ns) to the Tile PreProcessor system in the counting rooms, requiring a total data bandwidth of 40 Tbps. The TilePPr will store the detector data in pipeline memories to meet the new ATLAS Trigger and Data Acquisition architecture requirements, and will interface with the FELIX system and the first level trigger system.

Performance of the ATLASPix1 pixel sensor prototype in ams aH18 CMOS technology for the ATLAS ITk upgrade

Monolithic active pixel sensors (MAPS) based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the ATLAS Inner Tracker upgrade. Particles are detected using deep n-wells on a p-type substrate as sensor diodes with the depleted region extending into the silicon bulk. With readout electronics and sensor integrated on the same device, the detector complexity and the material budget are greatly reduced. The ATLASPix1 pixel sensor prototype is a large-scale MAPS prototype that implements the full readout chain on a single physical chip. It features a large in-pixel sensor electrode and is produced using the ams aH18 high voltage technology. Three pixel matrices with different readout architectures, triggered and untriggered, and pixel designs are implemented. We show the performance of one of the pixel matrix variants for samples irradiated up to 1015 1MeV meq/cm2.