Abstract
This paper analyzes the impact of column bus parasitic parameters on the output noise and response speed of the pixel signal in large-array CMOS image sensor (CIS), and the optimized column bus design scheme has been obtained. By building the mathematical model of the column bus, the relationship between output noise, response speed and the size of the column bus is revealed, and the influence of the column bus size on the sensor is evaluated by system impact factor (SIF). In 110 nm CMOS process and a 12.45 cm (H) × 12.45 cm (V) pixel array, the double-ended readout architecture is utilized for output noise and response time analysis. Average output noise (146 μV) and response time (6.35 μs) are attained at column bus width of 0.5 μm. The experimental results show that for a given pixel array, the increase of the column bus width will cause output noise reduction and a longer response time. In the chip design, the column bus size could be optimized according to the relationship between output noise, response speed and pixel array size given in the paper.
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