Readout Architecture Research Articles

Charge-injection Device Imaging of Sirius with Contrast Ratios Greater than 1:26 Million

The intrinsic nature of many astronomical objects, such as binary and multiple systems, exoplanets, circumstellar and debris disks, and quasar host galaxies, introduces challenging requirements for observational instrumentation and techniques. In each case, we encounter situations where the light from bright sources hampers our ability to detect surrounding fainter targets. To explore all features of such astronomical scenes, we must perform observations at the maximum possible contrast ratios. Charge-injection devices (CIDs) are capable of potentially exceeding contrast ratios of (i.e., 1 part in 1 billion) due to their unique readout architectures and inherent anti-blooming abilities. An on-sky testing of a commercially available CID, SpectraCAM XDR (SXDR), demonstrated raw contrast ratios from sub-optimal ground-based astronomical observations that imposed practical limits on the maximum achievable contrast ratios using CIDs. Here, we demonstrate the extreme contrast ratio imaging capabilities of the SXDR using observations of Sirius with the 1.0 m Jacobus Kapteyn Telescope, La Palma, Spain. Based on wavelet-based analysis and precise photometric and astrometric calibrations, we report a direct contrast ratio of Δm r = 18.54, , or 1 part in 26 million. This is an order of magnitude higher compared to the previous CID results.

Real-Time Sensing with Multiplexed Optomechanical Resonators.

Nanoelectromechanical resonators have been successfully used for a variety of sensing applications. Their extreme resolution comes from their small size, which strongly limits their capture area. This leads to a long analysis time and the requirement for large sample quantity. Moreover, the efficiency of the electrical transductions commonly used for silicon resonators degrades with increasing frequency, limiting the achievable mechanical bandwidth and throughput. Multiplexing a large number of high-frequency resonators appears to be a solution, but this is complex with electrical transductions. We propose here a route to solve these issues, with a multiplexing scheme for very high-frequency optomechanical resonators. We demonstrate the simultaneous frequency measurement of three silicon microdisks fabricated with a 200 mm wafer large-scale process. The readout architecture is simple and does not degrade the sensing resolutions. This paves the way toward the realization of sensors for multiparametric analysis with an extremely low limit of detection and response time.

Reservoir Computing Approach to Quantum State Measurement

Efficient quantum state measurement is important for maximizing the extracted information from a quantum system. For multi-qubit quantum processors in particular, the development of a scalable architecture for rapid and high-fidelity readout remains a critical unresolved problem. Here we propose reservoir computing as a resource-efficient solution to quantum measurement of superconducting multi-qubit systems. We consider a small network of Josephson parametric oscillators, which can be implemented with minimal device overhead and in the same platform as the measured quantum system. We theoretically analyze the operation of this Kerr network as a reservoir computer to classify stochastic time-dependent signals subject to quantum statistical features. We apply this reservoir computer to the task of multinomial classification of measurement trajectories from joint multi-qubit readout. For a two-qubit dispersive measurement under realistic conditions we demonstrate a classification fidelity reliably exceeding that of an optimal linear filter using only two to five reservoir nodes, while simultaneously requiring far less calibration data \textendash{} as little as a single measurement per state. We understand this remarkable performance through an analysis of the network dynamics and develop an intuitive picture of reservoir processing generally. Finally, we demonstrate how to operate this device to perform two-qubit state tomography and continuous parity monitoring with equal effectiveness and ease of calibration. This reservoir processor avoids computationally intensive training common to other deep learning frameworks and can be implemented as an integrated cryogenic superconducting device for low-latency processing of quantum signals on the computational edge.

1/f Noise Characteristics of Waveguide-Integrated PbTe MIR Detectors and Impact on Limit of Detection

The noise power spectral density of a detector is essential for determining the frequency of operation and readout architecture that yields an optimal signal-to-noise ratio. In this work, we characterize a waveguide-integrated PbTe mid-infrared detector and report on its noise spectrum, highlighting the presence of a current-dependent 1/f term dominating at low frequency and/or high bias over the Johnson component typical of a photoconductor. This behaviour, together with the substantially flat frequency response in the range between 1 kHz to 1 MHz, guide towards a lock-in readout strategy, that allows one to operate in the region of minimum noise without penalties in the detection performance. Practical guidelines to optimize the readout resolution are provided and the limit of detection of a gas sensing system exploiting PbTe photoconductors is derived, as an example of how a careful co-design of sensors and electronics can dramatically improve the detection performance.

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection mechanism using a radioactive source. These results prove that the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify that it can work up to about 3 Gbps, while they also indicate that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ ( IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values.

Coherent sensing performance comparison of framed and asynchronous GMAPD arrays.

Single photon counting Geiger mode avalanche photodiode (GMAPD) arrays are typically used for high-resolution 3D ranging. These high-gain, high-bandwidth detectors are also feasible for coherent sensing. GMAPD arrays have two different readout architectures: asynchronous and synchronous (or framed). The individual pixels in asynchronous GMAPD arrays operate independently, reducing the loss due to blocking during the reset time. In contrast, framed GMAPD arrays are prone to saturation as they reset the entire array of pixels simultaneously. This study presents a performance comparison of asynchronous and framed GMAPD arrays for coherent sensing as a function of common system parameters. Expressions for the arm probability and blocking loss are defined to contrast the mechanisms of missed detection opportunities for both types of GMAPD detectors.

MPV—Parallel Readout Architecture for the VME Data Acquisition System

Mountable controller with parallelized VERSA Module Eurocard (VME) (MPV) is a VME-compatible system having a parallel readout architecture. This article presents the system architecture and its data acquisition performance. In this system, the readout sequence is implemented in a field-programmable gate array (FPGA) to achieve the ideal VME bus speed. Data from multiple VME slave modules are read out in parallel, merged, and sent to a server. Maximum data throughput of 400 Mbps was achieved. Thus, the MPV system can dramatically improve the performance of VME data acquisition systems.

Signal and Noise Analysis of an Open-Circuit Voltage Pixel for Uncooled Infrared Image Sensors

An imaging pixel unit-cell topology leveraging a photodetector in the forward-bias region is proposed. Connecting the anode of the photodiode to the gate of a NMOS device operating in the subthreshold region provides the basis for a new open-circuit voltage pixel (VocP) architecture. Theoretical analysis is presented to show the response and performance benefits of the VocP in comparison to a conventional pixel. Based on this analysis, the signal and noise relationships for both pixels are derived and leveraged to construct an end-to-end readout system model. The model results highlight potential performance benefits of the VocP over a conventional direct-injection pixel topology. To verify the analysis, the proposed VocP readout architecture is fabricated along with a conventional direct-injection pixel readout in a $0.18~\mathrm {\mu }\text{m}$ CMOS technology. The VocP performance is compared to a traditional reverse-bias current-mode photodetector configuration. Simulation, modeling, and measurements align with the proposed analytical model. Benefits in system sensitivity and dynamic range are demonstrated showing more than a $2\times $ improvement in noise-equivalent temperature difference and a 4 dB improvement in dynamic range.

Scalable electronic readout design for a 100 ps coincidence time resolution TOF-PET system

We have developed a scalable detector readout design for a 100 ps coincidence time resolution (CTR) time of flight (TOF) positron emission tomography (PET) detector technology. The basic scintillation detectors studied in this paper are based on 2 × 4 arrays of 3 × 3 × 10 mm3 ‘fast-LGSO:Ce’ scintillation crystals side-coupled to 6 × 4 arrays of 3 × 3 mm2 silicon photomultipliers (SiPMs). We employed a novel mixed-signal front-end electronic configuration and a low timing jitter Field Programming Gate Array-based time to digital converter for data acquisition. Using a 22Na point source, >10 000 coincidence events were experimentally acquired for several SiPM bias voltages, leading edge time-pickoff thresholds, and timing channels. CTR of 102.03 ± 1.9 ps full-width-at-half-maximum (FWHM) was achieved using single 3 × 3 × 10 mm3 ‘fast-LGSO’ crystal elements, wrapped in Teflon tape and side coupled to a linear array of 3 SiPMs. In addition, the measured average CTR was 113.4 ± 0.7 ps for the side-coupled 2 × 4 crystal array. The readout architecture presented in this work is designed to be scalable to large area module detectors with a goal to create the first TOF-PET system with 100 ps FWHM CTR.

Frequency-Division Multiplexing with Graphene Active Electrodes for Neurosensor Applications.

Multielectrode arrays are used broadly for neural recording, both in vivo and for ex vivo cultured neurons. In most cases, recording sites are passive electrodes wired to external read-out circuitry, and the number of wires is at least equal to the number of recording sites. We present an approach to break the conventional N-wire, N-electrode array architecture using graphene active electrodes, which allow signal upconversion at the recording site and sharing of each interface wire among multiple active electrodes using frequency-division multiplexing (FDM). The presented work includes the design and implementation of a frequency modulation and readout architecture using graphene FET electrodes, a custom integrated circuit (IC) analog front-end (AFE), and digital demodulation. The AFE was fabricated in 0.18 μm CMOS; electrical characterization and multi-channel FDM results are provided, including GFET-based signal modulation and IC/DSP demodulation. Long-term, this approach can simultaneously enable high signal count, high spatial resolution, and high temporal precision to infer functional interactions between neurons while markedly decreasing access wires.

Fully Depleted Monolithic Active Microstrip Sensors: TCAD Simulation Study of an Innovative Design Concept.

The paper presents the simulation studies of 10 m pitch microstrips on a fully depleted monolithic active CMOS technology and describes their potential to provide a new and cost-effective solution for particle tracking and timing applications. The Fully Depleted Monolithic Active Microstrip Sensors (FD-MAMS) described in this work, which are developed within the framework of the ARCADIA project, are compliant with commercial CMOS fabrication processes. A set of Technology Computer-Aided Design (TCAD) parametric simulations was performed in the perspective of an upcoming engineering production run with the aim of designing FD-MAMS, studying their electrical characteristics, and optimizing the sensor layout for enhanced performance in terms of low capacitance, fast charge collection, and low-power operation. A fine pitch of 10 m was chosen to provide high spatial resolution. This small pitch still allows readout electronics to be monolithically integrated in the inter-strip regions, enabling the segmentation of long strips and the implementation of distributed readout architectures. The effects of surface radiation damage expected for total ionizing doses of the order of 10 to 10 krad were also modeled in the simulations. The results of the simulations exhibit promising performance in terms of timing and low power consumption and motivate R&D efforts to further develop FD-MAMS; the results will be experimentally verified through measurements on the test structures that will be available from mid-2021.

A universal 3D imaging sensor on a silicon photonics platform.

Accurate three-dimensional (3D) imaging is essential for machines to map and interact with the physical world1,2. Although numerous 3D imaging technologies exist, each addressing niche applications with varying degrees of success, none has achieved the breadth of applicability and impact that digital image sensors have in the two-dimensional imaging world3-10. A large-scale two-dimensional array of coherent detector pixels operating as a light detection and ranging system could serve as a universal 3D imaging platform. Such a system would offer high depth accuracy and immunity to interference from sunlight, as well as the ability to measure the velocity of moving objects directly11. Owing to difficulties in providing electrical and photonic connections to every pixel, previous systems have been restricted to fewer than 20 pixels12-15. Here we demonstrate the operation of a large-scale coherent detector array, consisting of 512 pixels, in a 3D imaging system. Leveraging recent advances in the monolithic integration of photonic and electronic circuits, a dense array of optical heterodyne detectors is combined with an integrated electronic readout architecture, enabling straightforward scaling to arbitrarily large arrays. Two-axis solid-state beam steering eliminates any trade-off between field of view and range. Operating at the quantum noise limit16,17, our system achieves an accuracy of 3.1millimetres at a distance of 75metres when using only 4milliwatts of light, an order of magnitude more accurate than existing solid-state systems at such ranges. Future reductions of pixel size using state-of-the-art components could yield resolutions in excess of 20megapixels for arrays the size of a consumer camera sensor. This result paves the way for the development and proliferation of low-cost, compact and high-performance 3D imaging cameras that could be used in applications from robotics and autonomous navigation to augmented reality and healthcare.

A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

Layered CMOS SPADs for Low Noise Detection of Charged Particles

This paper reports the characterization of SPAD arrays fabricated in a 150 nm CMOS technology in view of applications to the detection of charged particles. The test vehicle contains SPADs with different active area and operated with different quenching techniques, either passive or active. The set of devices under test (DUTs) consists of single-tier chips, about 30 mm2 in area, with dual-tier structures where two chips are face-to-face bump bonded to each other. In the dual-layer structure obtained in this way, the coincidence signal between overlapping SPAD pairs is read out, with a beneficial impact on the dark count noise performance. The DUT characterization was mainly focused on studying the breakdown voltage in the single-layer arrays and the dark count rate (DCR), measured in different working conditions, in both the single- and the dual-layer structures. Comparison between the DCR performance of the two configurations clearly emphasizes the advantage of the coincidence readout architecture.

A low-power, high-resolution, adaptive sensitivity readout circuit with selective detection range for capacitive biosensors

In this paper, the design and implementation of a low-power, high-resolution, fully differential readout architecture for capacitive sensing applications is presented. The proposed sensing mechanism is based on the gain variations of two capacitively coupled operational transconductance amplifiers (OTAs). The target analyte acts as the dielectric of a sensing electrode, and its detection results in capacitance variations. These capacitance variations are translated to voltage, and the result is amplified to be used as a biomarker detector. With high-gain OTAs and a high-gain difference amplifier, the proposed mechanism achieves a high-resolution of 1aF, with a sensitivity of 290mV/fF. The proposed structure exhibits such a high-resolution while maintains an extremely low-power consumption of 6.6μW. Using perfectly matched elements with accurate layout, this structure is able to reduce the mismatch-based errors to less than 0.05%. An 8-bit control word adjusts the sensitivity and the detection range of the proposed structure which results in a wide dynamic range of 100dB. The main features of the proposed structure such as high-resolution, high-sensitivity, low-power consumption, selective capacitance detection range and adaptive sensitivity, make this readout mechanism an ideal solution for sensitive, low-power, and accurate life science biosensors.

IQ Photonic Receiver for Coherent Imaging With a Scalable Aperture

Silicon photonics (SiP) integrated coherent image sensors offer higher sensitivity and improved range-resolution-product compared to direct detection image sensors such as CCD and CMOS devices. Previous generation of SiP coherent imagers suffer from relative optical phase fluctuations between the signal and reference paths, which results in random phase and amplitude fluctuations in the output signal. This limitation negatively impacts the SNR and signal acquisition times. Here we present a coherent imager system that suppresses the optical carrier signal and removes non-idealities from the relative optical path using a photonic in-phase (I) and quadrature (Q) receiver via a 90∘ hybrid detector. Furthermore, we incorporate row-column read-out and row-column addressing schemes to address the electro-optical interconnect density challenge. Our novel row-column read-out architecture for the sensor array requires only 2N interconnects for N2 sensors. An 8×8 IQ sensor array is presented as a proof-of-concept demonstration with 1.2×10-5 resolution over range accuracy. Free-space FMCW ranging with 250 resolution at 1 distance has been demonstrated using this sensor array.

A Compact Chopper Stabilized Δ-ΔΣ Neural Readout IC With Input Impedance Boosting

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $\Delta $ - $\Delta \Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm2 per channel, an input-referred noise of 5.53 ± 0.36 $\mu \text{V}_{\mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $\text{M}\Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

The Data Acquisition System for the ATLAS Phase-II Tile Calorimeter Demonstrator

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at Large Hadron Collider (LHC). The TileCal readout system consists of about 10,000 channels. In 2025, the LHC will be upgraded leading into the High Luminosity LHC (HL-LHC). The HL-LHC will be capable to deliver an instantaneous luminosity up to seven times compared to the LHC nominal luminosity. The TileCal Phase-II upgrade will replace the majority of the on-detector and off-detector electronics using a new readout schema for the HL-LHC era. The on-detector electronics will digitize and transmit calorimeter signals to the off-detector electronics at the bunch crossing frequency. In the counting rooms, the off-detector electronics will store the digitized samples in pipelined buffers and compute reconstructed trigger objects for the first level of trigger. The TileCal Phase-II upgrade project has undertaken an extensive R&D program which includes the development of a Demonstrator module to evaluate the performance of the new clock and readout architecture for the HL-LHC. A Demonstrator module containing the upgrade on-detector readout electronics was built, tested during several test beam campaigns, and inserted into the ATLAS experiment. The Demonstrator module is operated and read out using a Tile PreProcessor (TilePPr) Demonstrator which enables backward compatibility with the present ATLAS Trigger and Data AcQuisition and the Timing, Trigger and Command systems. This contribution describes the components of the clock distribution and data acquisition system for the Demonstrator module, and its implementation in the ATLAS experiment.

A low noise current readout architecture with 160 dB transimpedance gain and 1.3 MHz bandwidth

This paper proposes a low-noise readout circuit with a noise floor of 11 fArms/sq(Hz) and a bandwidth of 1.3 MHz. The novel electrostatic discharge (ESD) leakage current cancellation stage allows the circuit to detect sub-pA range current input. A total trans-impedance gain of 160 dB is obtained by a current preamplification stage with a 100 × current gain followed by a transimpedance amplifier (TIA) with a 1 Mohm feedback resistive gain. The reader is designed in a 0.18 μm CMOS process and consumes 5.6 mW from a 1.8 V supply.