A Low-Complexity Hybrid Readout Circuit for Lidar Receiver

Abstract

This brief presents a low-complexity hybrid readout architecture that can extract both timing and amplitude information of the return pulse concurrently for a light detection and ranging radar (Lidar) receiver. To reconstruct the short return pulse, the core circuit of one sampling and storage array with an embedded time-to-digital converter (SSA-TDC) is proposed. Instead of relying on the conventional power-hungry high-speed ADC, it selectively samples the interested return pulse with high speed and stores the voltages for later quantization in the long idle interval. In the preceding stage of the SSA-TDC, the analog front-end circuit cascaded of a narrow-bandwidth transimpedance amplifier, a voltage amplifier, and an equalizer circuit is included. The prototype chip of the eight readout channels is designed and fabricated with the 0.18- $\mu \text{m}$ CMOS process. The active circuit occupies an area of $1200\,\,\mu \text{m}\,\,\times 2100\,\,\mu \text{m}$ , and the power consumption of one single channel is 45 mW with 3.3-V supply. The proposed SSA-TDC has achieved a dynamic error of 180 ps in the experimental study.