Readout Architecture Research Articles

Advances in the Goertzel Filter Bank Channelizer for Cryogenic Sensors Readout

Neutrino mass estimation experiments and cosmic microwave background (CMB) radiation surveys both employ low-temperature detectors (LTD) known as calorimeters and bolometers, respectively. These detectors operate typically between 10 and 300 mK. LTDs multiplexed by means of a microwave superconducting quantum interference device multiplexer (µMUX) demonstrated to be an excellent device for the readout of several detectors in the microwave region. This entails generating a multi-tonal signal and its subsequent readout. A single-tone detection method based on a Goertzel filter bank (GFB) channelizer was used for the readout of the aforementioned signal, implemented in a software-defined radio readout architecture within a field-programmable gate array. The measurements presented here demonstrate remarkable results in validating the suitability of the GFB channelizer for this system.

Upgrade of the LHCb RICH detectors and characterization of the new opto-electronics chain

The LHCb detector has been upgraded to manage a five-fold increase in the instantaneous luminosity delivered to the experiment during LHC Run 3 and to readout data at the full bunch crossing rate of 40 MHz. The enhanced LHCb RICH detectors now feature Multianode Photomultiplier Tubes (MaPMTs), covering a total area of approximately 4 square meters, and brand-new frontend electronics to comply with the trigger-less readout architecture. The opto-electronics chain is capable of detecting single photons at repetition rates of up to 100 MHz/cm2 while maintaining an exceptionally low noise. The RICH upgrade is comprehensively outlined, including details about the characterization and studies on the photon detection system. The stability and uniformity achieved by optimizing the parameters of the opto-electronics chain enable the RICH system to function successfully and to provide excellent charged hadron identification in high occupancy conditions.

A versatile and fast pixel matrix read-out architecture for MAPS

A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30µm. Post-layout simulations with realistic hit shapes and rates up to 200MHz/cm2 show that time stamping at the 20ns level can be achieved for a digital power cost below 10mW/cm2.

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

EventLFM: event camera integrated Fourier light field microscopy for ultrafast 3D imaging

Ultrafast 3D imaging is indispensable for visualizing complex and dynamic biological processes. Conventional scanning-based techniques necessitate an inherent trade-off between acquisition speed and space-bandwidth product (SBP). Emerging single-shot 3D wide-field techniques offer a promising alternative but are bottlenecked by the synchronous readout constraints of conventional CMOS systems, thus restricting data throughput to maintain high SBP at limited frame rates. To address this, we introduce EventLFM, a straightforward and cost-effective system that overcomes these challenges by integrating an event camera with Fourier light field microscopy (LFM), a state-of-the-art single-shot 3D wide-field imaging technique. The event camera operates on a novel asynchronous readout architecture, thereby bypassing the frame rate limitations inherent to conventional CMOS systems. We further develop a simple and robust event-driven LFM reconstruction algorithm that can reliably reconstruct 3D dynamics from the unique spatiotemporal measurements captured by EventLFM. Experimental results demonstrate that EventLFM can robustly reconstruct fast-moving and rapidly blinking 3D fluorescent samples at kHz frame rates. Furthermore, we highlight EventLFM’s capability for imaging of blinking neuronal signals in scattering mouse brain tissues and 3D tracking of GFP-labeled neurons in freely moving C. elegans. We believe that the combined ultrafast speed and large 3D SBP offered by EventLFM may open up new possibilities across many biomedical applications.

Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation.

Closed-loop neuromodulation is emerging as a more effective and targeted solution for the treatment of neurological symptoms compared to traditional open-loop stimulation. The majority of the present designs lack the ability to continuously record brain activity during electrical stimulation; hence they cannot fully monitor the treatment's effectiveness. This is due to the large stimulation artifacts that can saturate the sensitive readout circuits. To overcome this challenge, this work presents a rapid-artifact-recovery time-multiplexed neural readout frontend in combination with backend linear interpolation to reconstruct the artifact-corrupted local field potentials' (LFP) features. Our hybrid technique is an alternative approach to avoid power-hungry large-dynamic-range readout architectures or large and complex artifact template subtraction circuits. We discuss the design and measurements of a prototype implementation of the proposed readout frontend in 180-nm CMOS. It combines time multiplexing and time-domain conversion in a novel 13-bit incremental ADC, requiring only 0.0018 mm2/channel of readout area despite the large 180-nm CMOS process used, while consuming only 4.51 μW/channel. This is the smallest reported area for stimulation-voltage-compatible technologies (i.e. ≥ 65 nm). The frontend also yields a best-in-class peak total harmonic distortion of -72.6 dB @2.5-mVpp input, thanks to its implicit DAC mismatch-error shaping property. We employ the chip to measure brain LFP signals corrupted with artifacts, then perform linear interpolation and feature extraction on the measured signals and evaluate the reconstruction quality, using a set of sixteen commonly used features and three stimulation scenarios. The results show relative accuracies above 95% with respect to the situation without artifacts. This work is an ideal candidate for integration in high-channel-count true closed-loop neuromodulation systems.

A vision chip with complementary pathways for open-world sensing.

Image sensors face substantial challenges when dealing with dynamic, diverse and unpredictable scenes in open-world applications. However, the development of image sensors towards high speed, high resolution, large dynamic range and high precision is limited by power and bandwidth. Here we present a complementary sensing paradigm inspired by the human visual system that involves parsing visual information into primitive-based representations and assembling these primitives to form two complementary vision pathways: a cognition-oriented pathway for accurate cognition and an action-oriented pathway for rapid response. To realize this paradigm, a vision chip called Tianmouc is developed, incorporating a hybrid pixel array and a parallel-and-heterogeneous readout architecture. Leveraging the characteristics of the complementary vision pathway, Tianmouc achieves high-speed sensing of up to 10,000 fps, a dynamic range of 130 dB and an advanced figure of merit in terms of spatial resolution, speed and dynamic range. Furthermore, it adaptively reduces bandwidth by 90%. We demonstrate the integration of a Tianmouc chip into an autonomous driving system, showcasing its abilities to enable accurate, fast and robust perception, even in challenging corner cases on open roads. The primitive-based complementary sensing paradigm helps in overcoming fundamental limitations in developing vision systems for diverse open-world applications.

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. The second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

AstroPix4 — a novel HV-CMOS sensor developed for space based experiments

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm2 can currently not be reached due to the digital consumption of 3.08 mW/cm2, while the analog power consumption of 1.04 mW/cm2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

Monolithic integration of superconducting-nanowire single-photon detectors with Josephson junctions for scalable single-photon sensing

We demonstrate superconducting single-photon detectors (SPDs) that integrate signals locally at each pixel. This capability is realized by the monolithic integration of superconducting-nanowire SPDs with Josephson electronics. The motivation is to realize superconducting sensor elements with integrating capabilities similar to their CMOS-sensor counterparts. The pixels can operate in several modes. First, we demonstrate that photons can be counted individually, with each detection event adding an identical amount of supercurrent to an integrating element. Second, we demonstrate an active gain control option, in which the signal added per detection event can be dynamically adjusted to account for variable light conditions. Additionally, the pixels can either retain signal indefinitely to record all counts incurred over an integration period, or the pixels can record a fading signal of detection events within a decay time constant. We describe additional semiconductor readout circuitry that will be used in future work to realize scalable, large-format sensor arrays of superconducting SPDs compatible with CMOS array readout architectures.

Model and analysis of the data readout architecture for the ITS3 ALICE Inner Tracker System

The ALICE collaboration is developing the Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm × 93 mm. ITS3 requires all hits from a particle flux of 5.75 MHz/cm2 to be transmitted on-chip to one of the sensor edges. This on-chip readout must balance the resources of power consumption, dead area, and readout performance by tuning different design parameters such as on-chip memories or on-chip links bandwidth. For doing so, a model of the ITS3 on-chip readout architecture will be presented. This model combines an accurate simulation of the particle flux fluctuations expected in ALICE with a clock-accurate digital readout simulator, combining high accuracy with fast code in terms of simulation speed.

High-rate, high-resolution single photon X-ray imaging: Medipix4, a large 4-side buttable pixel readout chip with high granularity and spectroscopic capabilities

The Medipix4 chip is the latest member in the Medipix/Timepix family of hybrid pixel detector chips aimed at high-rate spectroscopic X-ray imaging using high-Z materials. It can be tiled on all 4 sides making it ideal for constructing large-area detectors with minimal dead area. The chip is designed to read out a sensor of 320 × 320 pixels with dimensions of 75 μm× 75 μm or 160 × 160 pixels with dimensions of 150 μm× 150 μm. The readout architecture features energy binning of the single photons, which includes charge sharing correction for hits with energy spread over adjacent pixels. This paper presents the specifications, architecture, and circuit implementation of the chip, along with the first electrical measurements.

A monolithic active pixel sensor with node-based, data-driven, parallel readout for the high energy physics experiment vertex detector

We present the design of a prototype MAPS sensor MIC6_V1 based on a 55 nm Quad-well CMOS Image Sensor process for the CEPC vertex detector. A new node-based, data-driven, parallel readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. The size of MIC6_V1 is 2.8 mm × 2.8 mm, which contains a pixel matrix of 64 rows by 64 columns, and the pixel size is 23.6 μ m × 20 μ m. The integration time is 5 μs, and the hit arrival time measurement accuracy is 10 ns.

Modeling of CMOS Integrated Strain Sensors and Sensitivity Enhanced Readout Architecture

Modeling of CMOS Integrated Strain Sensors and Sensitivity Enhanced Readout Architecture

A 64-pixel mid-infrared single-photon imager based on superconducting nanowire detectors.

A large-format mid-infrared single-photon imager with very low dark count rates would enable a broad range of applications in fields like astronomy and chemistry. Superconducting nanowire single-photon detectors (SNSPDs) are a mature photon-counting technology as demonstrated by their figures of merit such as high detection efficiencies and very low dark count rates. However, scaling SNSPDs to large array sizes for mid-infrared applications requires sophisticated readout architectures in addition to superconducting materials development. In this work, an SNSPD array design that combines a thermally coupled row-column multiplexing architecture with a thermally coupled time-of-flight transmission line was developed for mid-infrared applications. The design requires only six cables and can be scaled to larger array sizes. The demonstration of a 64-pixel array shows promising results for wavelengths between 3.4 μm and 10 μm, which will enable the use of this single-photon detector technology for a broad range of new applications.

Beam test of a 180 nm CMOS Pixel Sensor for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix, based on a column drain readout architecture, has been developed to address the need for high spatial resolution. In order to evaluate the performance of the TaichuPix-3 chips, a beam test was carried out at DESY II TB21 in December 2022. Meanwhile, the Data Acquisition (DAQ) for a multi-plane configuration was tested during the beam test. This work presents the characterization of the TaichuPix-3 chips with two different processes, including cluster size, spatial resolution, and detection efficiency. The analysis results indicate the spatial resolution better than 5µm and the detection efficiency exceeding 99.5% for TaichuPix-3 chips with the two different processes.

Functional characterization of modules for the Silicon Tracking System of the CBM experiment

The CBM experiment is a fixed-target heavy-ion physics experiment at the future FAIR facility, designed to explore the QCD phase diagram at high baryon-net densities and moderate temperatures. To address its complex physics program, the experiment is conceived to operate at beam–target interaction rates up to 10 MHz with self-triggered front-end electronics and free-streaming readout architecture. The Silicon Tracking System (STS) of CBM is the main charged-particle tracker, capable of delivering time-stamped hits for online tracking and event building, and momentum measurement inside a superconducting dipole magnet. The functional unit of the STS is the detector module, a device assembled from a double-sided silicon microstrip sensor connected via a stack of microcables to a pair of front-end boards carrying the readout electronics. The assembly and successful operation of STS modules, produced with close-to-final components, was an important milestone achieved in recent years. The systematic study of the modules’ performance is also necessary for optimizing the assembly procedure and ensuring high production yield. This work reports a series of tests, which aim to evaluate the module’s operation and establish the basic criteria for quality control. It summarizes the procedures and results of different measurements performed with the modules, starting with noise estimation and charge amplitude calibration, resulting in the linearization of the channel’s ADC and a homogeneous threshold distribution. Those results were verified using a radioactive source. Additionally, first conclusions concerning the assembly yield in terms of number of functional channels were obtained. These studies represent a fundamental step towards the series production readiness for the final STS detector.

MALTA-Cz: a radiation hard full-size monolithic CMOS sensor with small electrodes on high-resistivity Czochralski substrate

Depleted Monolithic Active Pixel Sensor (DMAPS) sensors developed in the Tower Semiconductor 180 nm CMOS imaging process have been designed in the context of the ATLAS ITk upgrade Phase-II at the HL-LHC and for future collider experiments. The “MALTA-Czochralski (MALTA-Cz)” full size DMAPS sensor has been developed with the goal to demonstrate a radiation hard, thin CMOS sensor with high granularity, high hit-rate capability, fast response time and superior radiation tolerance. The design targets radiation hardness of > 1015 (1 MeV) neq/cm2 and 100 Mrad TID. The sensor shall operate as tracking sensor with a spatial resolution of ≈ 10 μm and be able to cope with hit rates in excess of 100 MHz/cm2 at the LHC bunch crossing frequency of 40 MHz. The 512 × 512 pixel sensor uses small collection electrodes (3.5 μm) to minimize capacitance. The small pixel size (36.4 × 36.4 μm2) provides high spatial resolution. Its asynchronous readout architecture is designed for high hit-rates and fast time response in triggered and trigger-less detector applications. The readout architecture is designed to stream all hit data to the multi-channel output which allows an off-sensor trigger formation and the use of hit-time information for event tagging.The sensor manufacturing has been optimised through process adaptation and special implant designs to allow the manufacturing of small electrode DMAPS on thick high-resistivity p-type Czochralski substrate. The special processing ensures excellent charge collection and charge particle detection efficiency even after a high level of radiation. Furthermore the special implant design and use of a Czochralski substrate improves the sensor's time resolution. This paper presents a summary of sensor design optimisation through process and implant choices and TCAD simulation to model the signal response. Beam and laboratory test results on unirradiated and irradiated sensors have shown excellent detection efficiency after a dose of 2 × 1015 1 MeV neq/cm2. The time resolution of the sensor is measured to be σ = 2 ns.

Characterization of a CMOS Pixel Sensor prototype for the CEPC vertex detector

The proposed Circular Electron Positron Collider poses significant challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor prototype, named TaichuPix, has been developed based on a column drain readout architecture. The performance of the second version of this prototype, TaichuPix2, has been evaluated using a radioactive source, which exhibits a time walk of less than 100ns corresponding to the threshold of 380 e− and amplitude variation of analog output from 300mV to 500mV. An infrared laser setup is utilized to estimate the single-point spatial resolution of this sensor for minimum-ionizing particles. The setup includes a high-precision three-dimensional translation stage and an optical system with a 1064nm laser diode. With this setup, the spatial resolution is estimated to be about 4µm. The performance for real particles is to be confirmed in a test beam.

Data Compression Versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording.

Future high-density and high channel count neural interfaces that enable simultaneous recording of tens of thousands of neurons will provide a gateway to study, restore and augment neural functions. However, building such technology within the bit-rate limit and power budget of a fully implantable device is challenging. The wired-OR compressive readout architecture addresses the data deluge challenge of a high channel count neural interface using lossy compression at the analog-to-digital interface. In this article, we assess the suitability of wired-OR for several steps that are important for neuroengineering, including spike detection, spike assignment and waveform estimation. For various wiring configurations of wired-OR and assumptions about the quality of the underlying signal, we characterize the trade-off between compression ratio and task-specific signal fidelity metrics. Using data from 18 large-scale microelectrode array recordings in macaque retina ex vivo, we find that for an event SNR of 7-10, wired-OR correctly detects and assigns at least 80% of the spikes with at least 50× compression. The wired-OR approach also robustly encodes action potential waveform information, enabling downstream processing such as cell-type classification. Finally, we show that by applying an LZ77-based lossless compressor (gzip) to the output of the wired-OR architecture, 1000× compression can be achieved over the baseline recordings.