A versatile and fast pixel matrix read-out architecture for MAPS

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A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30µm. Post-layout simulations with realistic hit shapes and rates up to 200MHz/cm2 show that time stamping at the 20ns level can be achieved for a digital power cost below 10mW/cm2.