Radiation-hardened Design Research Articles

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

With the continuous reduction of feature size of transistors, single-event triple-node-upsets (TNUs) induced by the striking of radiation particles in nano-scale CMOS circuits have emerged as a significant reliability concern. To address the shortcomings of existing radiation-hardened designs, including low reliability and high overhead, this paper proposes a cost-effective and highly robust TNU self-recovery latch design called DOCTRL. The proposed DOCTRL latch primarily consists of six dual-output C-elements (DOCs) and two clocked DOCs. By utilizing DOCs with two independent outputs, the proposed DOCTRL latch achieves a smaller area overhead. In addition, a four-level circular interlock matrix connection is designed to recover all possible TNUs within the proposed DOCTRL latch. Meanwhile, the latch also incorporates clock gating technology and a high-speed path to minimize power consumption and delay penalties. Simulation results indicate that the proposed DOCTRL reduces area by an average of 32.43 %, power consumption by 46.84 %, delay by 14.43 %, and area-power-delay product (APDP) by 69.55 %, compared to the five typical TNU self-recovery latches (SCLCRL, TNUSH, LCTNUCR, ADTRL, TSRL). Furthermore, detailed process, voltage, temperature (PVT), and Monte Carlo simulations verify the robustness of the proposed DOCTRL latch.

RADIATION HARDNESS OF INTEGRATED CIRCUITS: ESSENTIAL CONSIDERATIONS FOR SPACE APPLICATIONS

Radiation poses significant challenges to the reliability and performance of integrated circuits (ICs) deployed in space applications. The harsh space environment exposes ICs to various types of ionizing radiation, including solar particle events, cosmic rays, and trapped radiation belts, which can induce transient and permanent damage to semiconductor devices. Understanding the effects of radiation on ICs is essential for designing robust and reliable spaceborne electronics. This paper provides a comprehensive overview of the radiation effects on ICs, including single-event effects (SEEs), total ionizing dose (TID) effects, and dose rate effects. Strategies for mitigating radiation-induced failures, such as radiation-hardened design techniques and radiation testing methodologies, are also discussed. By addressing the essential considerations for radiation hardness in ICs, this paper aims to facilitate the development of reliable electronics for space missions.

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

Integrating Commercial-Off-The-Shelf Components into Radiation-Hardened Drone Designs for Nuclear-Contaminated Search and Rescue Missions

This paper conducts a focused probabilistic risk assessment (PRA) on the reliability of commercial off-the-shelf (COTS) drones deployed for surveillance in areas with diverse radiation levels following a nuclear accident. The study employs the event tree/fault tree digraph approach, integrated with the dual-graph error propagation method (DEPM), to model sequences that could lead to loss of mission (LOM) scenarios due to combined hardware–software failures in the drone’s navigation system. The impact of radiation is simulated by a comparison of the total ionizing dose (TID) with the acceptable limit for each component. Errors are then propagated within the electronic hardware and software blocks to determine the navigation system’s reliability in different radiation zones. If the system is deemed unreliable, a strategy is suggested to identify the minimum radiation-hardening requirement for its subcomponents by reverse-engineering from the desired mission success criteria. The findings of this study can aid in the integration of COTS components into radiation-hardened (RAD-HARD) designs, optimizing the balance between cost, performance, and reliability in drone systems for nuclear-contaminated search and rescue missions.

Machine learning based prediction model for single event burnout hardening design of power MOSFETs

Aiming at the interaction between different hardening techniques and the search for the optimal hardening scheme, we propose a machine learning based prediction model for single event burnout (SEB) hardening design of power MOSFETs in this paper. The feedforward neural networks are used to build the prediction model, which covers at least three commonly used SEB hardening techniques considering their interaction and predicts the variations in the radiation tolerance and the critical electrical parameters under the complex hardening conditions. Then, based on the prediction model, we can search for the optimal value of each hardening parameter to obtain the optimal hardening scheme, for which the radiation hardness can be greatly improved while keeping the critical electrical parameters at an acceptable level using the search algorithm. The prediction model proposed in this paper provides a new research method for the radiation hardening design of aerospace electronic devices, and it effectiveness has been successfully verified by the TCAD simulations.

Parametric Study of Cavity IEMP Responses in a Cylinder by Coupling Monte Carlo Method and 3-D Electromagnetic Particle-in-Cell Method

Internal electromagnetic pulse generated inside a cavity, known as Cavity IEMP, would disturb or damage sensitive electronic systems inside a spacecraft when illuminated by transient X-rays. To ensure their normal operations, accurate prediction and analysis of Cavity IEMP responses are required. In this article, the physical phenomena involved in three-dimensional (3-D) Cavity IEMP problems are numerically studied, including the interaction process between X-rays and the cavity wall material and the self-consistent process involving the motion of electrons and the evolution of electromagnetic fields. The interaction process is simulated with the Monte Carlo method to obtain the actual emission characteristics of forward electrons emitted into a cavity, including their yields, energy, and angular spectra, while the self-consistent process is simulated with a proposed 3-D electromagnetic particle-in-cell method to solve electromagnetic fields generated inside a cavity, whose driving forces are forward electrons with the calculated emission characteristics. This method fully considers electrons with different energies and directions and their impacts on the generated electromagnetic fields. With such method, the electromagnetic field distribution inside a cylinder exposed to transient X-rays is discovered based on the actual emission characteristics of X-ray-induced forward electrons. Furthermore, as forward electron emission characteristics are determined by properties of X-rays and cavities, the impacts of the blackbody temperature in X-ray energy spectrum, the cylinder wall thickness, and the cylinder wall material on the intensity of generated electric fields are fully explored. Based on the results, several suggestions are given to protect electronic systems in cavities against the electromagnetic coupling from Cavity IEMP. The study would guide radiation hardening design of electronic systems in spacecraft.

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications.

The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption.

New Insight Into Total-Ionizing-Dose Effect-Induced Breakdown Voltage Degradation for SOI LDMOS: Irradiation Charge Field Modulation

In this article, the concept of irradiation charge field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> ) is proposed to provide a new insight into total-ionizing-dose (TID) effect-induced breakdown voltage (BV) degradation for high-voltage silicon-on-insulator (SOI) lateral double-diffused metal–oxide-silicon (LDMOS). A unified explanation on TID-induced BV degradation is given that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> exerts modulation on net electric field, changing the relationship between lateral BV (BVL) and vertical BV (BVV). <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> would weaken electric field at silicon side of silicon/buried oxide interface and enhance that at oxide side, resulting in BVV increasing monotonously. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> would also weaken surface electric field at drain side and enhance that at source side, resulting in BVL changing with two potential trends: monotonic descent and nonmonotonic descent, corresponding to different initial surface breakdown points. Eventual BV degradation is determined by the combined result of BVV and BVL changing. Based on the new insight, a radiation hardening design strategy is proposed. Nonuniform initial surface electric field distribution with single drain peak is pursued, breaking the conventional optimization principle. Nonmonotonic descent of BV is achieved to enhance TID tolerance and verified by the developed 80-V SOI LDMOS with the proposed radiation hardening strategy.

Comparative analysis of radiation tolerant analog circuit layout in 180 nm CMOS technology for space application

This work extend the application of radiation hard by design(RHBD) techniques to circuit level and review the effectiveness of these methods based on performance of analog domain circuit in radiation environment. A 3D TCAD tool was used in simulating the different layout styles of NMOS device. The parameter like Ioff (off state leakage current), Ion(on state current), Vdsat( saturation voltage), Vth (threshold voltage), Ro (output resistance) and gm (trans-conductance) were in focus. A test chip comprising of four opamp circuits and implemented using different layout method(conventional, Half ring, Butterfly, ELT) . The test chip was fabricated in SCL’s 180 nm process and total ionization dose(TID) tolerance testing up to 300K rad was done. The findings of the work as follows: half ring and butterfly layout styles perform at par with ELT in TID tolerance test. The bandwidth and slew rate metrics of opamp employing half ring and butterfly layout were better by 25% and offer better trade-off in terms of silicon area. The quiescent current in opamp circuit implemented with RHBD technique increases by 3% but 16% increment observed for opamp circuit implemented with conventional method for radiation dose of 300K rad. The presented work can provide insights to designers for selecting the RHBD techniques for rad hard application specific integrated circuit (ASIC) design for space/defense applications.

Effects of 60Co γ ray radiation on the transmission characteristics of interconnection structures for 3D packaging

PurposeConcerning the radiation effects on the three-dimensional (3D) packaging in space environment, this study aims to investigate the influence of the total dose effect on the transmission characteristics of high-frequency electrical signals using experimental and simulation methods.Design/methodology/approachThis work carries out the irradiation test of the specimens and measures their S21 parameters before and after irradiation. A simulation model describing the total dose effect was built based on the experimental test results. And, the radiation hardening design is evaluated by the simulation method.FindingsThe experimental results demonstrate that the S21 curve of the interconnection decreases with the increase of the irradiation dose, indicating that the total dose effect leads to the decline of its signal transmission characteristics. According to the simulation results, decreasing the height of the through silicon via (TSV), increasing the radius of the TSV, reducing the length of Si and increasing the number of grounded through silicon via have positive effects on improving the radiation resistance of the interconnection structure.Originality/valueThis work investigates the effect of radiation on the transmission characteristics of interconnection structures for 3D packaging and proposes the hardening design methods. It is meaningful for improving the reliability of 3D packaging in space applications.

Novel radiation-hardened latch design for space-radiation environments

Novel radiation-hardened latch design for space-radiation environments

Numerical Analysis of SGEMP Responses on Coaxial Cables Based on a New Mesh Tally in Monte-Carlo Methods

System-generated electromagnetic pulse (SGEMP) that is generated by X-ray irradiation on coaxial cables would deteriorate sensitive electronic systems inside spacecraft, thereby affecting normal operations and survival of spacecraft. In this article, the SGEMP responses on coaxial cables are numerically assessed by using an equivalent transmission line model. In the transmission line model, a key parameter for determining its input is the charge distribution on coaxial cables due to X-ray irradiation. To acquire the actual charge distribution on coaxial cables, we present a new mesh tally in an in- house Monte-Carlo software, JMCT. The new mesh tally counts the number of charges in the user-defined mesh cells for coaxial cables to evaluate their nonuniform actual charge distribution, which has the advantages of high computational efficiency and high flexibility, and further yields a more accurate input to predict the SGEMP responses on coaxial cables. To illustrate the accuracy of the proposed method, it is validated by simulating the charge distribution on a coaxial cable and its load currents in the X-ray illumination and comparing the results with those calculated by using the method presented in the reference. In addition, the proposed method is further applied to explore the effects of coaxial cables’ structural parameters on their load currents. The studies in this article would guide the radiation-hardened design of coaxial cables.

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10^{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.

Crystal Fibers for the LHCb Calorimeter Upgrade

The Large Hadron Collider beauty (LHCb) experiment is one of the four main particle detectors located at the Large Hadron Collider. After the high-luminosity upgrade of the accelerator, the expected radiation dose faced by the LHCb electromagnetic calorimeter will reach peak values of 1 MGy in the centermost part, an amount not tolerable by the currently employed Shashlik technology, which demands a novel radiation hard design. In addition, a time resolution of few tens of picoseconds and a cell lateral size of about 2 cm are planned for track reconstruction purposes by the collaboration. In this article, the crystal spaghetti design was evaluated, a sampling geometry where scintillating crystal fibers are embedded in the dense absorbing material. The prototype was tested at CERN super proton synchrotron (SPS) with muons and electrons measuring an energy resolution of 3% for electrons at 20 GeV, tilting the prototype by 3° both horizontally and vertically with respect to the incident beam, and a time resolution of 79 ps. The results presented in this article show the feasibility of the design.

New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

Statistical analysis on the effects of heavy ion irradiation on 65 nm bulk silicon MOS devices

In this paper, the effect of heavy ion irradiation on 65 nm bulk silicon MOS devices is experimentally investigated. Different performance degradation behaviour is observed due to the intrinsic random incident of heavy ions. After irradiation, the threshold voltage (Vth) shifts negatively and the largest Vth shift is 54 mV. The drain induced barrier lowing (DIBL) effect deteriorates and DIBL increases by more than 30 mV V−1. The variation of maximum transconductance (Gm) is up to 30%. The off-state leakage current (Ioff) increases by several times, up to one order of magnitude. These performance degradation is attributed to the displacement damage in the active region, interface states at gate oxide interface and trapped charges in shallow trench isolation (STI) induced by micro-dose effect. Moreover, statistical analysis on the geometry dependence is firstly demonstrated. The average value of Vth shift, DIBL shift, and Ioff degradation increase with the decrease of gate width. Finally, the influence of technology downscaling from deep-submicron to nanoscale on the heavy ion irradiation effect is statistically analyzed. Four technology nodes (65 nm, 90 nm, 0.18 μm and 0.25 μm) are chosen for comparison. The results indicates that the Vth shift and DIBL shift increase with the technology downscaling. The Ioff degradation is strongly correlated with the trapped charge in STI caused by micro-dose effect. The results are helpful to further understand the single event effects of nanoscale bulk silicon MOS devices and may provide guideline for radiation-hardened design.

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.