Abstract
In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.
Highlights
Analog single-event transient (ASET) is an important topic for researchers who study radiation effects in integrated circuits (ICs) [1], which leads to disturbances of output signal characteristics and surrounding system responses
When the input voltage of the circuit is between 0.35 V and 0.55 V, the PMOS transistor works in the saturation region, and the amplifier works in the linear region
The peak voltage is determined by the charge collected by the device, M2 and M3 transistors, and the corresponding bias voltages Vb2 and Vb3
Summary
Analog single-event transient (ASET) is an important topic for researchers who study radiation effects in integrated circuits (ICs) [1], which leads to disturbances of output signal characteristics and surrounding system responses. The heavy ion moves through the sensitive area in analog circuits and generates movable charges which are controlled by drift, diffusion, and parasitic bipolar effect [4]. References [5,6,7] introduced redundancy techniques with multiple copies to reduce the effects of ion strikes on a single node in analog circuits. Those techniques reduce SET sensitivity but lead to large area and power penalty
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