Abstract
This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.
Highlights
Digital integrated circuits are important in many of today’s complex integrated circuits and systems
In mixed-signal circuits such as analog-to-digital converters (ADC), phase locked loops (PLL) and clock and data recovery (CDR), the digital logic is clocked at or a derivative of the mixed-signal sampling time which can be as high as several GHz in recent technologies
If only the flip-flops were allocated to their respective groups, unconstrained data-path cells might be placed in incorrect regions resulting in Multi-Bit Upsets (MBU) in the combinational logic
Summary
Digital integrated circuits are important in many of today’s complex integrated circuits and systems. TMR relies on the fact that only one logic signal can be upset at once and would fail if two out of three triplicated nets are upset This was less of a concern in old CMOS technologies where single particles only affected single digital cells. This method is the most reliable and uses the highest number of resources and power. A competing method is temporal time-redundancy [16] This smart approach does not triplicate the combinational logic but only triplicates flip-flops which are clocked with 3 delayed clocks [17].
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