Quantum Cost Research Articles

A new online testing technique for reversible circuits

Any technology offering zero power dissipation must be reversible. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥ 1. Analysing testability issues in a reversible circuit is an important phenomenon. A new online design-for-testability (DFT) technique for reversible circuits is proposed. The authors’ method yields less overhead in terms of quantum cost as compared to the previous online approaches.

Introduction to Reversible Logic Gates and its Operations

Abstract: Reversible logic is one of the most important issues at the moment and has a wide range of applications, such as low power CMOS, quantum computing, nanotechnol- ogy, cryptography, optical computing, DNA computing, and -digital signal processing (DSP), quantum Dot automata for mobile, communication, computer graphics. It is not possible to detect quantum computing without the implementation of a postponed brain operation. The main objectives of design are logical thinking to reduce quantum costs, circuit depths and the amount of waste disposal. This paper provides basic logical retrospective gates, which in the construction of a highly sophisticated system with retractable circuits as part of the old and unable to perform the most complex operations using quantum computers. Reversible circuits form the basic building block of quantum computers as all quantum functions are reversed. This paper presents data related to older retractable gates found in books and assists research in the design of complex computer circuits using retractable gates. Keywords: Defendable Logic, Portable Gate, Dismissal, Trash, Quantum Cost, Quantum-dot Cellular Automata, Reversible Computing, Reversible ALU, Flip Flop using Reversible Gates, Reversible Adder

Experimental study on the quantum search algorithm over structured datasets using IBMQ experience

In this work, a quantum search algorithm over structured datasets is proposed. Subsequently, the algorithm is executed on a real chip quantum computer developed by IBM Quantum experience (IBMQ). QISKit, the software platform developed by IBM, is used for the implementation of this algorithm. Quantum interference, quantum superposition, and π phase shift of the quantum state are applied in the proposed search algorithm. It performs a π phase shift on the initial state and conducts a state elimination and amplitude amplification process to reach the 'search key' or 'solution key' from the given structured dataset. The proposed quantum algorithm is executed using the QISKit SDK local backend ‘local_qasm_simulator’, real chip 'ibmq_16_melbourne', 'ibmq_belem' and 'ibmqx4′ IBMQ. The results suggest that the real chipibmq_16_melbourne is more quantum error- or noise-prone than ibmq_belem and ibmqx4. The correctness, validation, and application using the proposed algorithm are demonstrated. The algorithm is very promising in terms of low quantum cost and fewer gate requirements. This implies that the proposed quantum search algorithm may be a compelling and pertinent choice in the Noisy Intermediate-Scale Quantum (NISQ) technology era.

A new design for programmable logic array based on QCA-based nanotechnology

Dissipation in the complementary metal-oxide-semiconductor circuit size range has become a challenge for designers seeking to create a circuit with low power consumption and significantly reduced size. As a result, there is a need for an alternative technology that may provide revolutionary results. The quantum-dot cellular automaton is now widely regarded as a viable alternative to complementary metal-oxide-semiconductor technology. This paper demonstrates a new circuit for constructing a quantum-dot cellular automaton-based programmable logic array. The programmable logic array is a promising, standard, and fully programmable architecture that can use redundancy to make circuits with nanoscale feature sizes more practical. The comparisons based on cell number, size, and clock phases were made between the proposed circuit and previous ones using the QCADesigner. These comparisons verified the efficiency of the proposed design. The suggested programmable logic array circuit consists of 26 cells and occupies 0.04 µm2. In addition, the quantum cost of this circuit is 2.08, and the area delay is 0.08.

Quantum dot cellular automata using a one-bit comparator for QCA gates

Due to power dissipation, area, and reliability characteristics, CMOS technology has been influenced in nanosystems. Quantum DotCellular Automata(QCA) is a research project that studies alternative feasible systems that have similar capabilities. A 1-bit comparator was constructed using QCA nanotechnology. There are no crossovers in these circuits, making them simple to build. With a range of 74.81 to 99.87 percent improvement in performance, the new design is exceptionally efficient in terms of delay time, cell count, area, and the quantum cost. Thus, offered designs are typically found in different digital logics that demand a minimal amount of area and low power consumption. QCA Designer and QCA Designer E Tool are used to develop and simulate the 1-bit comparator circuits suggested here. The results show that the designed QCA 1-bit circuit requires 0.02 μm2 of area and 16 QCA cells. A delay of 0.5 clock is also obtainable. Compared to the other QCA circuits, the design of the QCA Comparator Circuit improves efficiency, cell count, delay, and cost.

A novel enhanced quantum image representation based on bit-planes for log-polar coordinates

Quantum image representation has a significant impact in quantum image processing. In this paper, a bit-plane representation for log-polar quantum images (BRLQI) is proposed, which utilizes $(n+4)$ or $(n+6)$ qubits to store and process a grayscale or RGB color image of $2^n$ pixels. Compared to a quantum log-polar image (QUALPI), the storage capacity of BRLQI improves 16 times. Moreover, several quantum operations based on BRLQI are proposed, including color information complement operation, bit-planes reversing operation, bit-planes translation operation and conditional exchange operations between bit-planes. Combining the above operations, we designed an image scrambling circuit suitable for the BRLQI model. Furthermore, comparison results of the scrambling circuits indicate that those operations based on BRLQI have a lower quantum cost than QUALPI. In addition, simulation experiments illustrate that the proposed scrambling algorithm is effective and efficient.

Design and simulation of QCA-based 3-bit binary to gray and vice versa code converter in reversible and non-reversible mode

The current Very Large-Scale Integration (VLSI) technology has reached its peak due to the fundamental physical limits of Complementary Metal-Oxide-Semiconductor (CMOS). Quantum-dot Cellular Automata (QCA) is considered a proper alternative to CMOS technology in digital circuit design. QCA has features like low power, small area, and high speed in nanoscale digital circuit design. A code converter is a circuit that converts a determined code to another one. Code converters such as Binary to Gray, Gray to Binary, and Binary to BCD converters have a crucial role in fast signal processing in digital systems. Also, code converters are used as a base unit for data transmission into the Arithmetic Logic Unit (ALU) to perform processes. A Binary-to-Gray converter converts the input data to a Gray number. In this paper, we propose a 3-bit Binary to Gray and vice versa code converter in QCA. Previous proposed designs could only convert Binary to Gray code or vice versa, but the proposed design convert both B2G and G2B codes into a circuit. We design our circuit in both reversible and non-reversible modes. The simulation of the proposed design is done using the QCADesigner 2.0.3 tools. The simulation results show that the proposed design is superior to the existing designs in terms of evaluation parameters such as cell count, area, latency, and quantum cost.

Negative controlled Fredkin gate circuits with mirrors

Data loss is a major problem in conventional circuits. But it cannot happen in reversible circuits. So energy dissipation per bit loss does not happen in this circuit. Also, recovery of input data can be possible in this circuit. Negative controlled Fredkin gate (NCF) is a self-invertible reversible gate. It performs SWAP operation if its control input is logic zero. In this paper, a mechanically controlled mirror-based NCF gate is designed, where the operation is based on the movement of mirrors. To move the mirror from its position electrical signal can be used. Optical signals are used in computational operations. Some complex reversible circuits viz. some logical operations (XOR-XNOR, AND-NAND, OR-NOR), DE-MUX/MUX, switching, and data shifting circuits are also shown in this paper. Quantum realization of the circuit was performed. Also, the matrix calculation was done to find out the operation of the circuit. Optical delay, optical cost, quantum delay, and quantum cost of every proposed design were calculated.

Realization of High-End Multiplexers and Demultiplexers using CSWAP Quantum Gate

CMOS technology is expected to come to an end in performance and accuracy due to limitations of the shirking of the transistors. To overcome these limitations, researchers are working towards the development of quantum circuits that provide high-speed processing. In this work, high-end quantum multiplexer and demultiplexer circuits are proposed using a controlled SWAP (CSWAP) gate with low quantum cost. The proposed circuits are implemented using quantum gates and simulated to reduce complexity and improve performance. The software tool used for the design and simulation of the proposed structures is IBM Qiskit with python coding. It is observed from the simulation results that the proposed multiplexers are improved by more than 28% compared with the existing designs available so far in the literature.

DESIGN OF ADDER AND SUBTRACTOR HAVING LESS POWER DISSIPATION

With the advancement in technology in the field of digital electronics, reversible logical has become a powerful tool in wide variety of areas like in designing of low power VLSI circuits, DNA computing, quantum computing and optical computing. Circuits made using reversible logic are more energy efficient and consumes less power. In these modern times we need designs of circuits that are speed efficient and should also consume less power. This paper emphasizes on presenting the improved reversible combinational circuit of eight – bit parallel adder and subtractor. These circuits are designed and implemented using Feynman, Double Feynman and MUX gates. Three designs of reversible eight – bit parallel adder and subtractor is proposed. Performance of all three designs is analyzed based number of reversible gates required, garbage input and output, quantum cost.

Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit

It is very important to detect and correct faults for ensuring the validity and reliability of these circuits. In this regard, a comparative study with related existing techniques is undertaken. Two techniques to achieve the testability of reversible circuits are introduced that have been improved in terms of quantum cost and fault coverage rate. Considering this aspect, the main focus of these techniques is on the efficient detection and location of faults with 100% accuracy. These techniques for fault detection in reversible circuit design, in addition to being able to produce the correct outputs, can also provide information for fault location that has already been done at a higher cost. Proposed approaches have been successfully tested for all types of SMGF, MMGF, PMGF, RGF, and SBF. In order to verify the functional correctness of the proposed scheme, it also has executed the testing over a reversible full adder circuit, and findings are checked. In the following, the proposed approach of reversible sequential circuits is presented for the first time so far. The cost metrics are evaluated for all the proposed designs and compared the estimated results against some existing design approaches of reversible circuits for better understanding.

Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q

Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.

Reversible Circuit Synthesis Method by Combining Factoring and Boolean Expression Diagram

<p indent="0mm">In order to reduce the cost of the resulting circuits, a reversible circuit synthesis method by combining factoring and Boolean expression diagram (BED) is proposed. For a given cover representing the exclusive-sum-of-products (ESOP) expansion of a Boolean function, cubes in the ESOP expansion represented by shared zero-suppressed multiple-output decision diagrams are first factored by leveraging algebraic division, then a BED is built from the factored ESOP cover and a reversible circuit is synthesized from the BED by mapping a BED node to a cascade of reversible gates. The proposed synthesis method is evaluated using benchmark functions. Experimental results show that the proposed synthesis method is time efficient. Compared to the existing reversible circuit synthesis methods using a directed acyclic graph as the representation model for Boolean functions, the proposed synthesis method can reduce the quantum cost and the number of qubits of the resulting reversible circuits in many cases. On average, compared to the synthesis method by combining variables grouping and BED, the proposed synthesis method can reduce the quantum cost and the number of qubits by 5.01% and 5.47%, respectively.

Reversible Gate Logic Adder with Parity Preserving Design

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Novel low quantum cost reversible logic based full adders for DSP applications

Novel low quantum cost reversible logic based full adders for DSP applications

Synthesis Strategy of Reversible Circuits on DNA Computers

DNA computers and quantum computers are gaining attention as alternatives to classical digital computers. DNA is a biological material that can be reprogrammed to perform computing functions. Quantum computing performs reversible computations by nature based on the laws of quantum mechanics. In this paper, DNA computing and reversible computing are combined to propose novel theoretical methods to implement reversible gates and circuits in DNA computers based on strand displacement reactions, since the advantages of reversible logic gates can be exploited to improve the capabilities and functionalities of DNA computers. This paper also proposes a novel universal reversible gate library (URGL) for synthesizing n-bit reversible circuits using DNA to reduce the average length and cost of the constructed circuits when compared with previous methods. Each n-bit URGL contains building blocks to generate all possible permutations of a symmetric group of degree n. Our proposed group (URGL) in the paper is a permutation group. The proposed implementation methods will improve the efficiency of DNA computer computations as the results of DNA implementations are better in terms of quantum cost, DNA cost, and circuit length.

A multi-commodity network model for optimal quantum reversible circuit synthesis.

Quantum computing is a newly emerging computing environment that has recently attracted intense research interest in improving the output fidelity, fully utilizing its high computing power from both hardware and software perspectives. In particular, several attempts have been made to reduce the errors in quantum computing algorithms through the efficient synthesis of quantum circuits. In this study, we present an application of an optimization model for synthesizing quantum circuits with minimum implementation costs to lower the error rates by forming a simpler circuit. Our model has a unique structure that combines the arc-subset selection problem with a conventional multi-commodity network flow model. The model targets the circuit synthesis with multiple control Toffoli gates to implement Boolean reversible functions that are often used as a key component in many quantum algorithms. Compared to previous studies, the proposed model has a unifying yet straightforward structure for exploiting the operational characteristics of quantum gates. Our computational experiment shows the potential of the proposed model, obtaining quantum circuits with significantly lower quantum costs compared to prior studies. The proposed model is also applicable to various other fields where reversible logic is utilized, such as low-power computing, fault-tolerant designs, and DNA computing. In addition, our model can be applied to network-based problems, such as logistics distribution and time-stage network problems.

A Review on Reversible Computing and it’s applications on combinational circuits

In this era of nanometer semiconductor nodes, the transistor scaling and voltage scaling are not any longer in line with each other, leading to the failure of the Dennard scaling. Thus, it poses a severe design challenge. Reversible computing plays a vital role in applications like low power CMOS, nanotechnology, quantum computing, optical computing, digital signal processing, cryptography, computer graphics andmany more. The primary reasons for designing reversible logic are diminishing the quantum cost, profundity of the circuits and the garbage outputs. It is impossible to determine the quantum computing without implementing the reversible computation. This paper will represent the literature survey based on several papers on combinational circuits using reversible computing and also the future scope is to be discussed.

Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing

Memory and its data communication are very significant in the Processor design and its performance. In order to attain high performance computing machine, the memory access has to be equally faster. Here in this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input / Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for nano-metric design of digital components. The functional simulation of Dual Port Memory design is verified using QCA. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are percentage of improvement in number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement in area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains 8.26% of area and 8.65 % of number of cells improvement. Moreover, the quantum circuits of the RAM are obtained and quantum cost, constant inputs, number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.