Abstract
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
Highlights
Reversible logic [1,2] is an essential part of building a reversible circuit
G Gatelibrary that can be used to synthesize any reversible circuit with n-input/output variables, 2.1.5
We proposed an efficient designs of reversible half and full addition and subtraction circuits
Summary
Reversible logic [1,2] is an essential part of building a reversible circuit. A circuit is called reversible if the circuit maps each input to an exclusive output, and the output contains enough information to retrieve the input, i.e., there is a one-to-one consistency among the input/output [3]. The reversible nature of quantum computers and quantum logic gates [14] demands the need to construct efficient reversible circuits, taking into consideration certain parameters [15], e.g., number of garbage output, quantum cost, number of constant inputs, gate count and delay. Arithmetic and logic unit (ALU) [16] is an essential part of any computational device It works as a multi-function circuit capable of performing a predefined set of logical and arithmetic operations. Several designs have been proposed for full adder and full subtractor reversible circuits. Gupta et al introduced an improved construction of full reversible adder/subtractor [18] using three F2G gates and a single MUX gate. The proposed designs are based on the G3 gate library [21] which, in turn, is capable of generating the permutation group of size 40,320 (23 !). The proposed designs are implemented and tested on IBM Q [24] using Python SDK [25] to measure the success probability of obtaining the correct results
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