Design of Parity Preserving Arithmetic and Logic Unit using Reversible Logic Gates

Abstract

Arithmetic and Logical Unit (ALU) is one of the key aspects of the digital world. In generally, it requires a colossal amount of power. This paper outlines a new design of one-bit Parity Preserving Reversible ALU circuit. To design the ALU with low power dissipation, we have used the concept of Reversible Logic computation. Conventional Circuits dissipate an enormous amount of power due to the loss of information bits in computation, but Reversible Circuits has no data loss as one on one mapping between outputs and inputs which leads to the minimization of power dissipation. In our design, we have used Parity Preserving Reversible Gates which are having Fault tolerance property as fault occurring at internal nodes results in an error at the output. So, Parity Preserving Reversible Gates is the one in which Output Parity remains same as of the Inputs. The aimed ALU has been carried out using Xilinx ISE 14.7 version software in Verilog HDL. To demonstrate the efficiency of proposed Parity Preserving Reversible Arithmetic and Logical Unit, each subpart is shown in terms of various parameters such as Quantum cost, Ancilla Inputs, Gate Count and Garbage Outputs and also a comparison with existing work is shown. The intended design is far better than the existing one because of its fault-tolerant capabilities. The proposed ALU extends its application over DNA mapping, Optical computation, cryptography, nanotechnology, quantum computing and digital signal processing.