Prototype Analog-to-digital Converter Research Articles

A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

This paper presents an AC-coupled, incremental analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural recording. It achieves a rail-to-rail electrode DC offset (EDO) rejection, low noise, a small area, and low power consumption. Fabricated in a 180 nm CMOS process, the prototype ADC achieves a high input impedance, 24 mVpp linear input range, and 58.9 dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 12 μW and an area of 0.0192 mm2. The referred-to-input (RTI) noise is 6.9 μVrms within the bandwidth of 1 Hz–10 kHz.

A High ENOB 14-Bit ADC without Calibration

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm ^2$</tex-math> </inline-formula> . With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm _w$</tex-math> </inline-formula> ) is 24.4 fJ/conversion-step.

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier

This article presents a bandwidth-adaptive pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The proposed amplifier embeds a high-gain three-stage FIA in the closed-loop operation, realizing an accurate interstage gain. It features dynamically scaled bandwidth, thereby offering fast settling, good stability, high energy efficiency, and low noise simultaneously. Its fully dynamic operation enables bandwidth and event rate adaptiveness. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 75.7 dB at 40 MS/s while consuming only 821 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W, resulting in a Walden figure-of-merit (FoM) of 4.1 fJ/conversion step. It attains a nearly consistent performance and scalable power over 100 times the sampling rate variation.

A 600-MS/s, 65-dB SNDR, 75-MHz BW Time-Interleaved Noise-Shaping SAR ADC

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) for wide bandwidth, high resolution, and low power consumption is proposed. A fully passive switched-capacitor integrator based on a single capacitor and a single-input comparator is adopted in the proposed three-channel structure for 1st-order noise shaping with low power consumption. The SAR conversion is split into coarse and fine conversions to allow noise shaping in the time-interleaved structure to maximize the bandwidth. In addition, a dynamic weight averaging method for three channels is introduced to suppress the effect of capacitor mismatch. The prototype ADC is implemented in a 28-nm CMOS process and achieves a signal-tonoise and distortion ratio of 65.37 dB, a bandwidth of 75 MHz at a sampling rate of 600 MHz, and a power consumption of 4.015 mW with a 1.1 V supply. A Walden figure-of-merit (FoM) of 17.65 fJ/conv.-step and a Schreier FoM of 168.1 dB show that the proposed TINS SAR ADC improves speed and accuracy with good power efficiency.

A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS.

This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm². The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier

This article presents a process, voltage, and temperature (PVT)-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier achieves a voltage gain of 16 with a two-stage configuration and high linearity over a wide temperature range with an on-chip timing generator. This work solves problems related to the low voltage gain and high temperature–sensitivity of the capacitively degenerated dynamic amplifier, while retaining the advantages of high linearity, wide output swing, and high energy efficiency. The prototype ADC is implemented in a 65-nm CMOS process and achieves 65-dB signal-to-noise-and-distortion ratio (SNDR) and 79.8-dB spurious free dynamic range (SFDR) at a sampling rate of 50 MS/s, while consuming only 0.46 mW. The power overhead of the timing generator is only 10% of the overall power consumption. It shows only 0.7-dB and 1.86-dB SNDR variations at 0.8–1.0-V supply variation and 0 °C–100 °C temperature variation, respectively.

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8–62.8 dB, with 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> than 1.7 dB, at 600–625 MS/s over −40° to 125° temperature range and 1.1–1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

This brief presents a single-loop third-order discrete-time delta-sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

This article presents a 60-MS/s 5-MHz BW noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an integrated highly linear input buffer in a 40-nm CMOS process. A dynamic level-shifting (DLS) technique is proposed to adaptively adjust the output common-mode voltage of the integrated input buffer for different operation phases, achieving the optimal linearity while alleviating the voltage breakdown problem at the capacitive digital-to-analog converter (CDAC) top plate. The mismatch-error-shaping (MES) technique is utilized to minimize the CDAC mismatch, which also generates undesired inter-symbol-interference (ISI) errors as a side effect. An ISI-error correction (IEC) technique is proposed to mitigate this problem and further improve the linearity. Both foreground and background calibrations are adopted in the subranging ADC and the NS filter to improve the gain accuracy. This SAR ADC prototype, with an integrated input buffer driving a 4.4-pF CDAC within 2.7 ns, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR)/total harmonic distortion (THD) of 85.4 dB/84.2 dB/97.3 dBc/86.4 dB/−92.9 dBc while consuming 8.06 mW from 2.5- and 1.1-V dual supply voltages. The Walden FoM (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {W}}$ </tex-math></inline-formula> ) and figure-of-merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula> ) are 60.6 fJ/conv.-step and 172.1 dB, respectively.

A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

This brief presents a 250 MS/s 12b successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The inverter-based preamplifier is introduced to suppress comparator noise. To improve the ADC robustness and speed, first, a cross-phase common mode feedback which explores the common mode voltage during the sampling phase, is proposed to address the PVT and input common mode voltage sensitivity of the inverter-based preamplifier. Second, a reconfigurable method is proposed to eliminate the long recovery time of the preamplifier at large input signals, as well as reduce the kickback noise at small input signals. Third, a PMOS pair with deliberate timing is introduced to accelerate the comparator regeneration without deteriorating its noise. The ADC employs 360 fF/side sampling capacitance and takes 2 ns conversion time to resolve 15 raw bits. Fabricated in 28 nm CMOS, the prototype ADC achieves 65.8 dB SNDR and 80.9 dB SFDR for a near-Nyquist input, occupies an active area of 0.01 mm2 and consumes a power of 4.7 mW, resulting in a Walden FOMW of 11.8 fJ/conv-step and a Schreier <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FOM}}_{{\boldsymbol{S}}}$ </tex-math></inline-formula> of 170.0 dB, respectively. Last but not least, the ADC attains a rail-to-rail input CM range.

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.2-11.7$ </tex-math></inline-formula> bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme

A low-power 12-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a reversible VCM-based capacitor (RVC) switching scheme is presented in this paper. The switching power consumption of the proposed scheme is 95% and 62.3% lower than that of conventional and VCM-based capacitor switching schemes, respectively. The use of a segmented DAC structure reduces the size of the largest capacitor from 211 unit capacitors in the conventional capacitor array to 24 unit capacitors. This 75% reduction in the capacitor area decreases the settling time of the DAC capacitor network as well as requirements on the bandwidth and driving capability of the reference source VREF. An ADC prototype with an active area of 0.218 mm2is fabricated in 180-nm 1P6M CMOS process. With supply of 1.8 V and sampling rate of 10 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 58.9 dB and consumes power of 0.36 mW, yielding a figure of merit (FOM) of 59.8fJ/conversion-step.

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 15.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {W}$ </tex-math></inline-formula> , resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.