A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier

Abstract

This article presents a bandwidth-adaptive pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The proposed amplifier embeds a high-gain three-stage FIA in the closed-loop operation, realizing an accurate interstage gain. It features dynamically scaled bandwidth, thereby offering fast settling, good stability, high energy efficiency, and low noise simultaneously. Its fully dynamic operation enables bandwidth and event rate adaptiveness. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 75.7 dB at 40 MS/s while consuming only 821 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W, resulting in a Walden figure-of-merit (FoM) of 4.1 fJ/conversion step. It attains a nearly consistent performance and scalable power over 100 times the sampling rate variation.