A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

Abstract

This brief presents a 250 MS/s 12b successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The inverter-based preamplifier is introduced to suppress comparator noise. To improve the ADC robustness and speed, first, a cross-phase common mode feedback which explores the common mode voltage during the sampling phase, is proposed to address the PVT and input common mode voltage sensitivity of the inverter-based preamplifier. Second, a reconfigurable method is proposed to eliminate the long recovery time of the preamplifier at large input signals, as well as reduce the kickback noise at small input signals. Third, a PMOS pair with deliberate timing is introduced to accelerate the comparator regeneration without deteriorating its noise. The ADC employs 360 fF/side sampling capacitance and takes 2 ns conversion time to resolve 15 raw bits. Fabricated in 28 nm CMOS, the prototype ADC achieves 65.8 dB SNDR and 80.9 dB SFDR for a near-Nyquist input, occupies an active area of 0.01 mm2 and consumes a power of 4.7 mW, resulting in a Walden FOMW of 11.8 fJ/conv-step and a Schreier <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FOM}}_{{\boldsymbol{S}}}$ </tex-math></inline-formula> of 170.0 dB, respectively. Last but not least, the ADC attains a rail-to-rail input CM range.