Proposed poly-Si TFT Research Articles

A low temperature processed Si-quantum-dot poly-Si TFT nonvolatile memory device

This paper reports on a successful demonstration of poly-Si TFT nonvolatile memory with a much reduced thermal-budget. The TFT uses uniform Si quantum-dots (size ∼ 10 nm and density ∼1011 cm−2) as storage media, obtained via LPCVD by flashing SiH4/H2 at 580 °C for 15 s on a Si3N4 surface. The poly-Si grain-enlargement step was shifted after source/drain formation. The NiSix-silicided source/drain enables a fast lateral-recrystallization, and thus grain-enlargement can be accomplished by a much reduced thermal-cycle (i.e., 550 °C/4 h). The excellent memory characteristics suggest that the proposed poly-Si TFT Si quantum-dot memory and associated processes are promising for use in wider TFT applications, such as system-on-glass.

A New RSD Poly-Si Thin Film Transistor With Inside Spacer Design

In this brief, a raised source/drain, accompanied with an inside spacer poly-Si thin film transistor (RSDIS-TFT) structure, has been proposed and discussed. The gate covered on an inside spacer can serve as a field plate and create a field-induced drain region to reduce the channel electric field. The proposed device has a lower drain electric field and can alleviate the kink effect. In addition, the leakage current can also be reduced. This is because this RSDIS structure can spread the electric field intensity out at the end of the drain, and decrease the drain electric field. Moreover, the device stability, such as the threshold voltage shift and transconductance degradation under a high gate bias, is improved by the design of raised source/drain and inside spacer structure. The lower drain electric field of the RSDIS-TFT is also beneficial to scaling down the device for a better performance. Therefore, the proposed poly-Si TFT is suitable to be used in active-matrix flat panel electronics.

A Novel Four-Mask-Processed Poly-Si TFT Fabricated Using Excimer Laser Crystallization of an Edge-Thickened<tex>$alpha$</tex>-Si Active Island

A four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 μm and a channel width of W = 1.2 μm possesses a high field-effect mobility of 260 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and an on/off current ratio of 2.31 × 10/sup 8/.

Gate Overlapped Lightly Doped Drain Poly-Si TFTs Employing 45° Tilt Implant For Source and Drain

ABSTRACTWe propose a short channel gate overlapped lightly doped drain (GOLDD) poly-Si TFT employing 45° tilt implant for source and drain (S/D) regions without any additional ion doping or mask. Oblique-incident ELA activation is performed to activate both n+ S/D and n- LDD regions as well as cure junction defects. The proposed poly-Si TFT can suppress the anomalous leakage current, and exhibit the better reliability against the hot-carrier stress.

46.3: High Performance Dual‐Gate and Multi Channel Poly‐Si TFTs fabricated by XeCl Excimer Laser Annealing on Selectively Floating a‐Si Thin Film

AbstractA high performance poly‐Si TFTs is fabricated by a new ELA method which employs floating a‐Si thin film structure and the effect of pre‐patterning. The proposed poly‐Si TFT exhibits high performance electrical characteristics which are high mobility of 504cm2/Vsec and low subthreshold slope of 0.337 V/dec.

28.1: High‐Mobility Poly‐Si TFTs Employing XeCl Excimer Laser Annealing on Selectively Floating a‐Si Thin Film

AbstractHigh‐mobility poly‐Si TFTs have been fabricated by a simple ELA method which employs a selectively floating a Si active layer. Large lateral grains exceeding 4μm have been grown. The proposed poly‐Si TFT exhibits a high field—effect mobility of 459cm2/Vsec due to the reduction of grain boundaries perpendicular to current path.

The Elimination of Ion Implantation Damage at the Source/Drain Junction of Poly-Si TFTs

AbstractWe report a new poly-Si TFT, of which the troublesome implantation damage near the source/drain junction was eliminated, by performing source/drain ion implantation as well as excimer laser annealing (ELA) prior to the gate formation. The recrystallization of a-Si in the channel region and the dopant activation in the source/drain region were simultaneously accomplished by single ELA process step so that the implantation damage, which results in large leakage current of TFT, has been successfully eliminated. TEM image verifies that large poly-Si grains were successfully grown from the ion implanted source/drain region to the channel region. The proposed poly-Si TFT, of which mobility is 171 cm2/Vs, exhibits a large on/off current ratio exceeding 4.1 × 107 without LDD or offset structure while those of the conventional TFT, which has been fabricated simultaneously for the comparison purpose, are 86 cm2/Vs and 6.1 × 106.

Short Channel Poly-Si TFT with Single Grain Boundary by Excimer Laser Annealing on Al-masked a-Si Layer

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.

A Novel Four Terminal Poly-Si Tft Suppressing Kink and Improving Reliability

ABSTRACTWe fabricated a new device, which employs counter-doped lateral body terminal (CLBT) in order to suppress kink effects and improve the device stability. Proposed device also employs a buried channel (BC), which increases ON-current and operating frequency. Although LDD structure is not employed in the proposed device, low OFF-current is successfully obtained due to elimination of minority carrier through CLBT. We have measured the dynamic properties of poly-Si TFT device and circuit. The reliability of TFT and circuits after AC stress is also discussed in our paper.The proposed poly-Si TFT has high ON-current and low OFF-current compared with conventional 3-terminal poly-Si TFT. The 4-terminal device characteristics were measured with source and CLBT shorted. The proposed device exhibits superior performance to conventional device in ON-current because BC prevents carrier scattering to gate oxide. We have performed bias and high temperature stress test of ring oscillator in order to investigate dynamic reliability between conventional poly-Si TFT and proposed 4-terminal poly-Si TFT. Our experimental results show that BC enables the device to have high mobility and switching frequency (33MHz at VDD=15V). The minority carrier elimination of CLBT suppresses kink effects and makes superb dynamic reliability of CMOS circuit.

Electrical characteristics of poly-Si TFT's with smooth surface roughness at oxide/poly-Si interface

We have fabricated a polycrystalline silicon thin film transistor (poly Si TFT) using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFT's fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength, and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to he critical to enhance the device performance.

A new poly-Si TFT to improve surface roughness at poly-oxide/poly-Si interface

We have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. The surface roughness at the interface is observed by transmission electron microscopy (TEM) and is also evaluated by atomic force microscopy (AFM) after the oxide layer is removed using buffered HF acid.Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.

Enhancement of On/Off Current Ratio of Poly-Silicon TFT by Selective Laser-Induced Crystallization of Active Layer

ABSTRACTWe have proposed the new poly-Si TFT which reduces the leakage current effectively by employing highly resistive a-Si region in the channel. The active layer of proposed device is crystallized selectively by employing excimer laser annealing while the both sides of channel near the source/drain are not recrystallized and remained as a-Si. Unlikely LDD or offset structure, the a-Si region which is designed to reduce the leakage current acts as the conduction channel of carriers under the ON state, so that the ON current is decreased very little. The selectively crystallized active layer can be fabricated by irradiating the excimer laser through ITO film of which transmittance at the wave length of laser is selectively adjusted. In the course of fabricating the proposed device, any additional photo masking step is not necessary and misalign problem is eliminated. The experimental results show that the ON/OFF current ratio of proposed poly-Si TFT is 106 while that of conventional one is 105.

A novel polysilicon thin-film transistor with a p-n-p structured gate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably.

The Poly-Si Tfts Fabricated by Novel Oxidation Method with Intermediate Oxide

AbstractWe have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.

Performance of Poly-Si Tfts with Double Gate Oxide Layers

AbstractWe have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.