Programmable Read Research Articles

A 2-Way Verification Process using One Time Password Key for Home Authentication System By IJISRT

The goal of this research project is to make it possible to implement extra security measures in place of employment and residence.In the suggested system, A 2- way verification technique is applied. First, the data is stored in the Electrically Erasable Programmable Read Only Memory (EEPROM) password for security. If the user enters the correct password, a randomized verification One Time Password or key is sent via paired Bluetooth and user device which is smartphone for 2 - way verification. If the entered key or OTP matches, the system will be opened and the required job may be begun. If either the key or the OTP is entered incorrectly, access is denied and the user can have a few attempts-- three chances under the suggested approach. The main objective is to develop a complete home security system using wireless devices and embedded (micro controller) technology.

EEPROM endurance degradation at different temperatures: State of the art TCAD simulation

Electrically Erasable Programmable Read Only Memory (EEPROM) is a widely used memory device, nowadays implemented in submicron technology nodes. In this paper we show how the well-known trapping power law found in the literature can be retrieved by combining well calibrated state of the art Technology Computer Aided-Design (TCAD) simulations with a compact model for tunnel oxide degradation during EEPROM cycling. We pinpoint how this approach can be used to predictively assess the programming window closure and consequently, considerably reduce the time-consuming cycling test procedure. Finally, we show how this methodology can cover a wide range of temperatures, making it very attractive for high demanding applications such as automotive.

Security Enhancement for Building Access, Using One Time Password (OTP) Technology

Ubiquitous as mobile technologies are, and the various advancements the technologies have experienced, makes the field pertinent for integration into security systems of buildings. As a security enhancement technique for building access, this project was proposed as a way of paving a way for integration of one time password (OTP) technology using microcontroller to security systems. In addition, the proposed project will be a supplement to the challenges of other security authentication methods centered on Bluetooth, radio frequency identification (RFID), biometrics and voice recognition techniques. In other to reduce complexity in design, a microcontroller was introduced to hub the coordination of the system. The two way verification system which can be coupled with aforementioned security systems, boast of its ability to store numeric identity of each authorized user to a building in the electrical erasable programmable read only memory (EEPROM) of the microcontroller. The system prompt a user wanting to gain access to the building through the door to input designated numeric identity (password) stored in data base. Once the inputted designated numeric identity entered matches an identity in the data base, then for the second verification process, a randomly generated OTP which has a programmed validity of three minutes is sent to the user phone via a GSM (global system for mobile communication) module. If either the password or OTP entered doesn’t match, then access is denied and the user will only be relegated to two limited successful chances with time duration as programmed for retrial before the system reset for the next user. Once there is failure at any stage of verification outside prescribed attempted limit, an alarm is sounded with implication that a burglar is attempting entry. Electric power to the project was driven from an ac mains which was then rectified to power all the dc dependent components used. The low construction cost, user friendliness, flexibility, insured security when compared to other security systems, makes the inovation unique.

Designing of an Efficient Electronic module for Sensory Network used in Smart City

(Please read carefully abstract of the template). Now-a-days the world population is rapidly increases for which a dreadful requirement is necessary for developing a livable city. Hence the term Smart City is introduced which focus on the Smart environment and environment development, smart waste management and sanitation, smart water management and harvesting, smart energy management etc. In order to monitoring the entire city in a smart way, all the related information is required to collected in an efficient manner. Hence, the Sensory Network operated in wireless mode is a best choice for collecting useful information in several points of the cities. Though, the sensory Network operated in wireless mode consumes a high power so the sovereignty of the module. This paper projected a designing of an efficient electronic circuit module which operate with less power for sensory network used in a smart city. The proposed module consists of a sensory module along with storage unit. The Sensory module operates in wireless mode is implemented by multi-channel Radio Frequency (RF) with a frequency range of 310 to 910 MHz and an External Memory as Electrically Erasable Programmable Read Only Memory (E2PROM) with Real Time Clock Chip (RTC-DS1307IC) is considered as storage unit. Finally, the designed module is operated by considering both the information from sensory nodes and storage unit.

Synthetic readers and writers for mammalian chromatin.

A study in Cell reports the development of a synthetic, modular and programmable read–write system that serves as a platform for programming epigenetic functions in mammalian cells and can aid the analysis of epigenetic regulatory mechanisms.

IOT Based Energy Meter Reading System with Automatic Billing

In recent time e-meter (electronic meter) place a major role for the power consumption &cost efficient system. In advanced future it has high reliable and productive programmed meter perusing framework (AMRS). This paper aims to plan a straightforward ease.IOTbased energy meter reading system which includes fault indication. Unit usage after (i.e. for 15 days once). Mode selection (automatic& manual) and SMS alert to user. Mode selection option is included. To avoid more power consumption automatic mode is used to cut-down the appliances for the user convenience. If there is a fault in the e-meter it sends a notification to the user. If there is any fault in E-meter the LED will glow. EEPROM (Electrically Erasable Programmable Read Only Memory) used as flash memory to store a data. The proposed system neglects the regular digital meter reading system and allows remotely access the electronic meter. Legitimate validation, user can get to the created webpage points of interest from anyplace on the planet. The advantages of this project are to reduce cost and save more power and also reduce man power and time consumption. This project is implemented is hardware and software used are ARUDINO IDE (using embedded C language).

A radiation-hardened programmable read only memory for space applications

A radiation-hardened programmable read only memory for space applications

Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory

A 200-KB embedded electrically erasable programmable read -only memory (EEPROM), which operates with a single 1.5-V power supply voltage based on an HHGRACE (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm EEPROM process, is developed. In this brief, several key design techniques are presented. An improved bit cell with a larger current sensing window is adopted in the split-source EEPROM array. To get high-speed read operation, a high-performance sense amplifier and a dynamic sensing window tracking reference voltage generating circuit have been proposed. The die size of the proposed EEPROM IP is 1.271 mm2, and the EEPROM cell size is 0.32 $\mu\text{m}^{2}$ . Access time of 30 ns is achieved at 1.5 V and 25 °C.

A Study on High Density Gate-Oxide Anti-Fuse PROM Memory Cell Program Features

The program consistency of high density gate-oxide anti-fuse PROM (programmable read only memory) memory cell is considered in this paper. To solve this problem, we do research on the mechanism and models of gate-oxide break down. A test chip based on 2T memory cell is also designed for the experiment. During the test, we have found that the program consistency of 2T cell is really pessimistic. What’s more, the program voltage has effect on the consistency. Through research and test, we have got the optimal program voltage-6.5V for 2T memory cell in 180nm technology. To further improve the consistency, we modify the 2T memory cell and propose a 3T memory cell. It consumes 18% more area, but the standard deviation of equivalent resistance decreases 15.3% in the worst situation. The deviation can decrease 80.3% at most. The program consistency is greatly improved.

Low Power CMOS Look-Up Tables using PROM

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm 2 layout area, which is less compared with 765.5 μm 2 produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

A Highly Scalable Single Poly-Silicon Embedded Electrically Erasable Programmable Read Only Memory With Tungsten Control Gate by Full CMOS Process

A highly scalable single poly-silicon multiple time programmable erasable programmable read only memory (EEPROM) with tungsten metallic control gate (W-CG) manufactured by full 0.13 μm-CMOS process is successfully demonstrated in this letter. Since the coupling ratio of conventional EEPROM cell is reduced with decreasing cell size, a smaller size in W-CG cell with a reduced spacing of CG to floating gate (FG) can obtain a higher coupling ratio and increase programming/erasing window owing to its novel lateral metal-insulator-poly coupling structure.

Temperature Monitoring and Logging System Suitable for Use in Hospitals, Incorporating GSM Text Messaging

In this paper, a microcontroller-based temperature monitoring and logging system suitable for use in hospitals was designed and constructed. The features include ability to monitor a patient’s temperature on a continuous basis while displaying the instant result on a Liquid Crystal Display (LCD) device. The temperature monitored is logged in a memory device, Electrically Erasable Programmable Read Only Memory (EEPROM), located in the system at every 10 minutes interval and can be interfaced with a computer using USB or RS232 UART device. An ATmega16 AVR is used as the heart of the control and coordination of all the activities of the individual modules. It allowed a doctor at location from the patient to keep track of his patient’s condition while attending to other issues .

Windows Mobile LiveSD Forensics

More and more often, smartphones are relevant targets of civil and criminal investigations. Currently, there are several tools available to acquire forensic evidence from smartphones. Unfortunately, most of these tools require to connect the smartphone under investigation through a cable to an external device, like a computer or a multimeter. Some tools even require to disassemble the chips from the smartphone board.In this paper, we propose LiveSD Forensics, an on-device live data acquisition solution, to acquire evidence from both the Random-Access Memory (RAM) and the Electronically Erasable Programmable Read Only Memory (EEPROM) of Windows Mobile Devices.To the best of our knowledge, LiveSD Forensics is the only tool that performs on-device live data acquisition of the RAM and the EEPROM of Windows Mobile Devices. LiveSD Forensics uses a standard SD-Card equipped with tailored code to perform the data acquisition. Compared to other existing tools, LiveSD also generates the smallest memory alteration. Finally, to assess the effectiveness of the proposed methodology, we test LiveSD in a practical scenario, that is retrieving from the RAM the cryptographic key used by a known on-the-fly encryption tool. Results support the quality and effectiveness of our proposal.

Comparative analysis of influence of gamma radiation on programmable memory characteristics

The aim of this paper is to examine the reliability of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) components subjected to the influence of gamma radiation. This problem is of considerable significance for both military industry and space technology. We present total dose results for the NM27C512 8F85 EPROM and M24128 – B W BN 5 T P EEPROM components. There is evidence that EPROM components radioactive reliability is better than that of EEPROM components. Furthermore, the changes EPROM's undergoes are reversible, so that after erasing process and reprogramming all EPROM components are fully functional. On the other hand, EEPROM's changes are irreversible and when subjected to the influence of gamma radiation, all EEPROM components become permanently nonfunctional. The obtained results are analyzed and explained via the interaction of gamma radiation with oxide layers.

Highly configurable capacitive interface circuit for tri‐axial MEMS microaccelerometer

A highly configurable capacitive interface circuit with on‐chip calibration capability for tri‐axial microaccelerometer is presented. The capacitive interface circuit is designed to be programmable, and can reduce the output errors due to the parasitic capacitance variations and process variations. The capacitive sensing chain adopts the chopper stabilisation, and includes the front‐end charge amplifier with three 10‐bit programmable capacitor arrays, 9‐bit digital‐to‐analogue converter and 10‐bit programmable gain amplifier. The calibration coefficients are stored to the on‐chip erasable programmable read only memory. The outputs from the three‐channel capacitive sensing chain are converted to digital signal by the integrated 14‐bit algorithmic analogue‐to‐digital converter. After calibrating the 48 samples, all the samples meet the desired specification range. Before the calibration, the errors of the average values of the output offset and gain were +47.1% and −85.9%, respectively. After the calibration, however, the errors of the average values of the output offset and gain are reduced to be 0.3% and 0.5%, respectively. The resolutions for x/y‐axis and z‐axis are measured to be 326 and 728 µg, respectively.

Computer-Aided TV Receiver Electrically Erasable Programmable Read Only Memory Eeprom Dumper

This study aimed to design a Computer-Aided TV Receiver EEPROM Dumper at the Bohol Island State University – Main Campus. The study utilized experimental design. There were Thirty (30) respondents composed of Twenty (20) BS Electronics III students and Ten (10) selected technicians who rated the device in terms of level of performance in the areas of Efficiency, Safety and Convenience of Use. The data gathered were treated statistically using weighted mean for rating and interpretation. Based on the interpretation of the results, the Description of Assembly was rated “Good” meaning the device can easily be assembled since the circuit included only few numbers of electronic components and followed a simple design. In the Level of Performance in terms of Efficiency, it was rated “Good” meaning the device was able to effectively diagnose EEPROM Chips problem. In term of Safety, it was rated “Good” which meant the device was safe to use and operate. In terms of Convenience of Use, it was also rated “Good” meaning the device was user-friendly. Based on the overall findings, the researchers concluded that the device can be a great help to the technicians in troubleshooting TV Sets and it is ready to be introduced to the market. Keywords - EEPROM, TV receiver, electrically erasable, programmable read only memory, eeprom chips, troubleshooting

Total dose characteristics of single poly EEPROM and SONOS EEPROM on SOI

Devices of single poly electrically ersable programmable read only memory (EEPROM) and silicon-oxide-nitride-oxide-silicon (SONOS) EEPROM on silicon on insulator (SOI) are fabricated on self-built 0.8 μm SOI process. And through a set of experiments on EEPROMs of these configurations and comparisons, SOI SONOS EEPROM is successfully developed with good and stable total dose radiation hardened characteristics. These provide stronger proofs to choose EEPROM in radiation hardened circuits.

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

To reduce the short-channel effect for memory cell transistors beyond 2× nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S-factor of 309 mV/decade, wide enough threshold voltage (Vth) window of 15 V between program and erase state, and fast enough program and erase time of 100 µs and 100 µs. And we observed no significant Vth-window narrowing and increase in Vth of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2× nm size NAND EEPROM.

A novel phase-coherent programmable clock for high-precision arbitrary waveform generation applied to digital ion trap mass spectrometry

Digital ion trap (DIT) mass spectrometry requires the ability to precisely and accurately produce waveforms. The quality of the mass spectra produced in terms of resolution and mass accuracy depend on the resolution and precision of the applied waveforms. This publication reveals a novel method for the production of arbitrary waveforms in general and then applies the method to the production of DIT waveforms. Arbitrary waveforms can be created by varying the clock frequency input to a programmable read only memory that is then input to a digital-to-analog converter (DAC). The arbitrary waveform is composed of a defined number of points that are triggered to be written after programmed numbers of clock cycles to define the arbitrary waveform. The novelty introduced here is that the direct digital synthesis (DDS) generated clock frequency can be precisely changed as the arbitrary waveform is written because we have developed a method to rapidly switch the DDS frequency exactly at the end of the output clock cycle allowing exact timing of multiple transitions to produce precise and temporally complex waveforms. Changing the frequency only at the end of the output clock cycle is a phase-coherent process that permits precise timing between each point in the arbitrary waveform. This waveform generation technique was demonstrated by creating a prototype that was used to operate a digital ion trap mass spectrometer. The jitter in the phase-coherent DDS TTL output that was used as the frequency-variable clock was 20 ps. This jitter represents the realizable limit of precision for waveform generation. The rectangular waveforms used to operate the mass spectrometer were created with counters that increased the arbitrary jitter to 100 ps. The mass resolution achieved was 5000 at m/ z = 414. Resolution should improve with increasing mass because the waveforms have longer periods while the jitter should remain constant. Given the current limit of the variable clock resolution, much better mass resolution should be achievable with future generations of the waveform production system. The agility of the DDS function generators permits the phase-coherent variable clock to be switched at a rate up to 250 MHz. This permits arbitrary waveforms to be produced with much more temporal complexity than previously possible.

TCAD-based demonstration of improved spacer select gate EEPROM cell architecture

An SSG EEPROM (Spacer Select Gate Electrically Erasable Programmable Read Only Memory) cell is proposed for improvement in program and erase operations and compared with a conventional one. Electrical characteristics of the conventional SSG EEPROM cell in program and erase operations are simulated, analyzed, using TCAD software tools, and verified against measurements. The improved SSG EEPROM cell reaches a target threshold voltage 3.9 V at 0.26 ms after the program operation starts, whereas the conventional cell at 1.7 ms. The Fowler–Nordheim tunneling current and floating gate charge of the improved EEPROM cell during the program operation are 5 times and 46% larger than those of the conventional cell, respectively. Scaling down the SSG EEPROM cells improves both the program and erase speeds. As the floating gate length of the conventional SSG EEPROM cell is reduced from 0.21 to 0.1 μm, the 0.1-μm EEPROM cell reaches the target program threshold voltage 25 times faster than the 0.21-μm cell.