Process, Voltage, Temperature Corner Research Articles

PVT Analysis and Behavioral Modeling of Doherty and Envelope Tracking RF ULP Power Amplifiers using 65 nm CMOS Technology

This research encompasses both Process-Voltage-Temperature (PVT) considerations and behavioral modeling of two proposed Power Amplifier (PA) designs for wireless communication systems. Process variations, supply voltage changes, and temperature changes provide difficulties for the design and optimization of power amplifiers for wireless communication systems and may have a substantial influence on their effectiveness. PVT analysis and behavioral modeling have been conducted to address the aforementioned challenges and characterize the behavior and performance of the power amplifiers under real-world operating conditions. It investigates the impact of process variations, supply voltage variations, and temperature variations on the performance of the PAs. The insights gained from this analysis contribute to a deeper understanding of the power amplifiers' performance, efficiency, and suitability for specific wireless communication standards, laying the foundation for future advancements in RF power amplifier design. The first design focuses on a Doherty PA (DPA) tailored for low-power short-range applications complying with the IEEE Wireless Personal Area Network (WPAN) standard. The second design explores an Envelope Tracking (ET) supply bias control for low-power long-range applications conforming to the IEEE Wireless Local Area Network (WLAN) standard. By examining these factors, the research ensures that the PAs exhibit reliable and optimal performance under real-world operating conditions. The PVT corners show a change in gain of only 0.4 dB for DPA and 0.9 dB for ET PA. Furthermore, behavioral modeling is employed to characterize the power efficiency of the envelope tracking PA, along with the current efficiency and quotient current on the load current scale. These models provide valuable insights into the behavior and performance of the PAs at a higher level of abstraction. The results and findings contribute to a deeper understanding of the PA’s performance, efficiency, and suitability for specific wireless communication standards, laying the foundation for future advancements in RF power amplifier design.

A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process

ABSTRACT The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC’s post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs.

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows

This brief proposes adaptive dither windows to calibrate bit weights in pipelined analog-to-digital converters (ADCs). It exploits the comparator meta-stability nature to construct dither windows, which avoids doubling the number of the comparators. The dither window size as defined by the sub-ADC comparator metastability region is tightly controlled and adapted to process-voltage-temperature (PVT) variations by adjusting the digitally controlled delay lines (DCDLs) against a capacitor-ratio reference. Besides, it cancels the voltage swing increment due to the dither windows, which relieves the design of the residue amplifier and saves the over-range margin of the stage. The proposed calibration technique is demonstrated by using a 12-bit pipelined ADC in a 40 nm CMOS process, and simulation results show that the window size is adjusted adaptively under PVT corners while the voltage swing increment is cancelled. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) are improved from 61.8 dB and 53 dB to 92 dB and 73.6 dB, respectively.

Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, <; 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

Delay Based Auto-Calibrated PVT Monitor System and Method

In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.

A Two-Speed, Radix-4, Serial–Parallel Multiplier

In this paper, we present a two-speed, radix-4, serial-parallel multiplier for accelerating applications such as digital filters, artificial neural networks, and other machine learning algorithms. Our multiplier is a variant of the serial–parallel (SP) modified radix-4 Booth multiplier that adds only the nonzero Booth encodings and skips over the zero operations, making the latency dependent on the multiplier value. Two subcircuits with different critical paths are utilized so that throughput and latency are improved for a subset of multiplier values. The multiplier is evaluated on an Intel Cyclone V field-programmable gate array against standard parallel–parallel and SP multipliers across four different process–voltage–temperature corners. We show that for bit widths of 32 and 64, our optimizations can result in a $1.42\times $ – $3.36\times $ improvement over the standard parallel Booth multiplier in terms of area–time depending on the input set.

A PVT-Robust Analog Baseband With DC Offset Cancellation for FMCW Automotive Radar

This paper presents a process-voltage-temperature (PVT)-robust analog baseband with DC offset cancellation (DCOC) for automotive radar applications. The baseband is composed of three stages of programmable gain amplifier (PGA) and an embedded fifth-order Butterworth filter. A novel embedded Gm-cell based DCOC feedback loop is proposed to achieve fine DC offset rejection and a low high-pass the cut-off frequency with an economic chip area. The proposed embedded Gm-cell based DCOC feedback topology is capable of improving gain error and loop stability simultaneously. Besides, a constant overdrive biasing technique is proposed to strengthen PVT robustness. Implemented in 65-nm CMOS technology, the measured results show that the analog baseband can provide a programmable gain range from 18.2 to 70.6 dB with 5.8 dB per step with a gain error of <;0.2 dB, while the 1-dB bandwidth range is from 200 kHz to 10 MHz. An OIP3 of 7.8 dBm and an input referred noise (IRN) of 15.8 nV/√Hz are obtained. The gain deviation is lower than 2.2 dB across all PVT corners. The core circuit consumes a dc power of 6 mW from a 1.2-V supply and occupies a chip area of 0.1 mm 2 .

A Highly Linear Wide-Band Tunable Lna for Military Radio Applications

A wide-band tunable Low-Noise Amplifier (LNA) was designed to be used in military radios. The LNA works in the frequency range of 30–512 MHz where military walkie-talkies operate. To cover the wide range of operating frequencies, the output of amplifier is divided into four sub-bands with four separate external inductors and integrated capacitor arrays. The first part of the study analyzes the performance parameters such as the gain, tuning, matching, noise figure, and distortion. Layout of the design was completed, and post-layout simulations, including the layout parasitic effects, were run to quantify the performance. The LNA achieves a minimum of 12-dB gain across the entire operating frequency range. The minimum rejections achieved by the LNA at 10% and 20% offset from the center-tuned frequency were 7 dB and 13 dB, respectively. The LNA achieves a worst-case noise figure of 4.6 dB, and the impedance-match parameter (S11) is better than −20 dB under all the conditions. The worst cases P1dB (1-dB Compression Point) and IIP3 (3rd Order Input Intercept Point) were 9.1 dBm and 18 dBm, respectively, across frequency and process–voltage–temperature corners. The design dissipates 20 mA from a 3.3-V power supply and uses a 1.5-V power supply for capacitor array termination.

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

A PVT detection and compensation technique is proposed to automatically adjust the slew rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output signal is adaptive. The proposed design is implemented using a typical 40nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460MHz given 0.9/1.8V supply voltage with a 20pF load. Particularly, the maximum slew rate improvement is 8%, the core area of the proposed design is 0.052×0.254mm2, the maximum slew rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.

A 2×VDD output buffer with PVT detector for slew rate compensation

A novel PVT (process, voltage, temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, supply voltage, and temperature (PVT) is detected, respectively. Based on the detected PVT corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 90nm CMOS process to justify the slew rate performance. By the on-silicon measurements, the slew rate of output signal is compensated over 26%, the maximum slew rate is 1.65 (V/ns), the maximum data rate is 330MHz given 1.2/0.9V supply voltage with a 20pF load, the core area of the proposed design is 0.056×0.406mm2, and the power consumption is 2.2mW at 330MHz data rate.

Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process–Voltage–Temperature Corner Analysis

Even for a single circuit, it has become increasingly time consuming to simulate at the SPICE level. However, the situation is getting worse when it comes to simulating thousands of such circuits, where often one circuit is closely related to another. This problem arises in applications such as process-voltage-temperature corner circuit simulation or simulation-in-the-loop circuit optimization. The traditional approach to solving this problem is to repeatedly invoke SPICE simulation on each of those circuits. Such an approach does not exploit the similarity among those circuits and could lead to prohibitively high computational cost. This paper presents a new simulation approach capable of simulating hundreds and thousands of closely related systems with the computational cost comparable to or even less than that of a few simulations, yet with the same simulation accuracy and robustness. The proposed approach is based on the combination of the LU-factorization-based direct method (used to construct preconditioners) and Krylov-subspace-based iterative methods (used to solve circuit equations) to explore the common characteristics shared by a set of closely related systems. The key novelty is a systematic method that uses the fewest direct solving for underlying linearized systems and then solves the rest using Krylov-subspace-based iterative methods, with preconditioners computed from those LU factors. In addition, a method of automatically constructing preconditioners from device equations has been developed based on model compilation and demonstrated on MOS transistor Berkeley short-channel IGFET model (BSIM) models. Several circuit examples are included to show the effectiveness of the proposed approach.