Abstract
This brief proposes adaptive dither windows to calibrate bit weights in pipelined analog-to-digital converters (ADCs). It exploits the comparator meta-stability nature to construct dither windows, which avoids doubling the number of the comparators. The dither window size as defined by the sub-ADC comparator metastability region is tightly controlled and adapted to process-voltage-temperature (PVT) variations by adjusting the digitally controlled delay lines (DCDLs) against a capacitor-ratio reference. Besides, it cancels the voltage swing increment due to the dither windows, which relieves the design of the residue amplifier and saves the over-range margin of the stage. The proposed calibration technique is demonstrated by using a 12-bit pipelined ADC in a 40 nm CMOS process, and simulation results show that the window size is adjusted adaptively under PVT corners while the voltage swing increment is cancelled. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) are improved from 61.8 dB and 53 dB to 92 dB and 73.6 dB, respectively.
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