A 10-bit 40MS/s pipelined ADC with pre-charged switched operational amplifier

Abstract

This paper describes a 10-bit 40MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82mW. The ADC is designed in a 1.8V 1P6M 0.18-µm CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19dB and Signal to Noise and Distortion Ratio (SNDR) of 60.25dB when a 19.02MHz sinusoidal signal is feed-in.