Priority Encoder Research Articles

Design and Implementation of Eight-Way Call System Based on Digital Integrated Circuits

This paper introduces the construction of an eight-channel call system using medical callers. The circuit enables the call signal to be sent to the 74HC148 priority encoder for encoding if any of the channels make a call. The encoded signal is processed by the 74LS283 and then output from the 74LS373 latch to the 4511BD decoding and driving circuit. The output of the decoding and driving circuit is displayed on the display circuit, showing the number of the channel that made the call. Meanwhile, the control signal triggers a monostable oscillator circuit composed of a 555 timer, which generates a temporary stable output signal with a pulse width of about 2s. The pulse signal drives a multivibrator circuit composed of a 555 timer, which causes the LED to work and output an alarm signal. The alarm state can be eliminated manually by pressing a key.

Design and Simulation of Balanced Ternary Priority Encoder

The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols i.e.−1,0 and 1. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from https://github.com/Aggtur11/Ternary-Logic-Simulator. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.

PICMIC-0: a 5 μm pitch hexagonal pixel sensor with an original tri-axis readout

We present in this paper a new sensor called PICMIC-0 that is intended to exploit the intrinsic spatial resolution of the MicroChannel Plate (MCP) detectors. Manufactured using 6-metal TowerJazz 180 nm wafer technology, the sensor features hexagonal charge collection pixels on the top metal layer with a pitch of 5 μm and covering an area of 7.4 × 6.4 mm2. The 2 million of the pixels of this sensor are not read out individually.Each pixel is connected to a straight-line in either 0°, 120° or -120° orientation, in which a current is produced in case of a hit. Each of these readout strip-lines is connected to a readout cell which receives this current, amplifies it using a current mirror and converts it into a digital signal by means of a current comparator. The data is collected from the digital outputs of the readout cells using a priority encoder readout scheme and transmitted in frames of 400 ns. This projective readout system reduces the number of channels to be read out from 2 million pixels to 2556 readout cells integrated within the pixel matrix. Using three projections reduces the ambiguity in case of multiple hits.

Reversible priority encoder in quantum-dot cellular automata

This paper presents a reversible structure for priority encoder. In order to expand the proposed design, the proposed structure is presented based on a modular method. For this purpose, first using the feature of insignificance of least-significant inputs when the value of most-significant input is one in the priority encoder, a special purpose reversible OR gate is introduced. Then, using this gate, we provide a reversible structure for the 4: 2 priority encoder. The proposed structure is designed entirely with reversible OR gates and inverter gates. We design the cell layout of this structure in QCADesigner software. In order to prove the modularity of the proposed design, the structure of 8: 3 reversible priority encoder is designed using 4: 2 reversible priority encoder.

Efficient Nano-Scale Design of TIEO Based Reversible Logic Toffoli Gate Priority Encoder in Quantum-Dot Cellular Automata

The goal of this research is to create a QCA-based reversible priority encoder. It is one of the most crucial parts of the encoding and decoding process. This novel nanotechnology, known as quantum-dot cellular automata (QCA), shows promise as a foundation for the development of reversible circuits. This paper proposes a simple, reversible, 4-2 line priority encoder design for the QCA platform. Using the simple and cheap Toffoli gate architecture, a reversible encoder circuit may be built. To analyze the proposed designs’ structural soundness, the simulation program QCA Designer is used.

Allosteric DNAzyme-based encoder for molecular information transfer

Dynamic DNA nanotechnology plays a significant role in nanomedicine and information science due to its high programmability based on Watson-Crick base pairing and nanoscale dimensions. Intelligent DNA machines and networks have been widely used in various fields, including molecular imaging, biosensors, drug delivery, information processing, and logic operations. Encoders serve as crucial components for information compilation and transfer, allowing the conversion of information from diverse application scenarios into a format recognized and applied by DNA circuits. However, there are only a few encoder designs with DNA outputs. Moreover, the molecular priority encoder is hardly designed. In this study, we introduce allosteric DNAzyme-based encoders for information transfer. The design of the allosteric domain and the recognition arm allows the input and output to be independent of each other and freely programmable. The pre-packaged mode design achieves uniformity of baseline dynamics and dynamics controllability. We also integrated non-nucleic acid molecules into the encoder through the aptamer design of the allosteric domain. Furthermore, we developed the 2n-n encoder and the Endo IV-assisted priority encoder inspired by immunoglobulin's molecular structure and effector patterns. To our knowledge, the proposed encoder is the first enzyme-free DNA encoder with DNA output, and the priority encoder is the first molecular priority encoder in the DNA reaction network. Our encoders avoid complex operations on a single molecule, and their simple structure facilitates their application in complex DNA circuits and biological scenarios.

Architectural analysis of 1-D to 2-D array conversion of priority encoder

Architectural analysis of 1-D to 2-D array conversion of priority encoder

Design, simulation and comparative analysis of carbon nanotube based energy efficient priority encoders for nanoelectronic applications

In the paper, innovative CNT based encoder and two priority encoders have been designed, simulated and compared with conventional CMOS encoder and priority encoders at 32 nm technology node. As the CMOS technology is continuously scaling down to physical limits of the device, several challenges come out related to scalability, reliability, short channel effects, leakage etc. To solve these issues of CMOS, CNT is one of the promising new technologies without sacrificing reliability and performance. The proposed CNT based encoder and priority encoders substantially outperformed CMOS based counterparts in Power, Delay and Power-Delay-Product.

Design and simulation of an all-optical priority encoder based on 2-D photonic crystal

Design and simulation of an all-optical priority encoder based on 2-D photonic crystal

Design of Sixteen-Input Priority Encoder with DNA Nano Switches

With the application of DNA computing in more and more fields, the tasks are becoming more and more complex, and the scale of DNA circuits is gradually increasing. However, the current investigation of largescale circuits of DNA molecules is still a challenge. So it is crucial to optimize the performance of large-scale DNA circuits. In this paper, a large-scale digital logic circuit 16-Input-5-Output Priority Encoder is realized by using the DNA nano switches for the first time. The simulation of the 16-Input-5-Output Priority Encoder circuit shows that this method solves the problems of NOT gate instability and optimizes the DNA circuit in terms of reaction time, circuit complexity, and experimental difficulty. This paper proves the feasibility and superiority of using DNA nano switches to realize large-scale circuits, provides a new idea for realizing large-scale DNA circuits, and brings new development for the application of DNA circuits in biosensor, DNA complex computing and other fields.

Design and simulation of a subwavelength 4-to-2 graphene-based plasmonic priority encoder

In this paper, a plasmonic waveguide including a sandwiched SiO2 channel between a graphene layer and a silicon ridge is designed. The surface plasmon polaritons are concentrated near the graphene and propagate along the graphene-SiO2 interface. By adjusting the chemical potential of graphene at 0.1 eV and 0.5 eV, the propagation loss of 486.3 dB/μm and 0.42 dB/μm is obtained for designing a plasmonic switch. The figure-of-merit for the designed waveguide is equal to 160. By getting the help of 6 waveguides and 2 combiners, a 4-to-2 plasmonic priority encoder is proposed. If two input signals are synchronously applied to an encoder, the priority feature is needed for corresponding to the higher priority input and providing the correct binary code at output ports. Considering the priority for inputs, all working states in four categories are simulated and the performance of the designed encoder is evaluated. The contrast ratio of 13.1 dB and the cross-talk of −16.22 dB are obtained for the working wavelength of 7 µm. The area of the presented encoder is 1.92 μm2, smaller than other works, promising for optical integrated circuits.

Modified priority encoder based hardware efficient N-bit comparator

ABSTRACT Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the ‘Encounter(R) RTL Compiler RC14.28’.

A novel proposal for all optical priority encoder using photonic crystal based nonlinear cavities

A novel proposal for all optical priority encoder using photonic crystal based nonlinear cavities

Ultra-fast all optical photonic crystal MVL decoder and encoder

In this paper, a general method is proposed to design all optical MVL decoder and encoders. The presented structures are composed of threshold detectors which are designed based on nonlinear photonic crystal ring resonator. The nonlinear optical Kerr effect has been used in the proposed structures to control the amount of transmission by input signal power. Therefore, input signal can be controlled so as to be passed or dropped in the threshold detector. Threshold value adjustment method is presented that is based on the radii of rods tuning. Plane wave expansion and finite difference time domain methods are used to simulate and analyze the proposed structures. The presented decoder and encoders occupy less than 278 µm2 and 1334 µm2 respectively. Simulation results show that the propagation delay of the proposed all optical ternary decoder and encoders are 1 ps and 2 ps respectively. The smallest contrast ratio for the logic 1- logic 0 in ternary decoder is 10 dB. The smallest contrast ratio for the logic 1 - logic 0 and for logic 2 - logic 0 in ternary encoder and priority encoder are 11.4 dB, 13.6 dB, 6.2 dB and 8.9 dB respectively.

Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures

Hardware security in single flux quantum (SFQ) circuits is an emerging research area due the increasing demand of data centers operating with sensitive information and the limited number of fabrication facilities, where certain stages can be compromised. An existing logic locking technique in SFQ circuits, that is based on supplying additional current with mutual inductance to change the circuit operation, is analyzed in this article. Two new attacks on this logic locking technique are proposed. In the first attack, the locked OR cell is reset by applying a specific input combination. As a result, the overall range of correct key values can be increased by approximately 18.8 and 32.9% depending on the location of the generated mutual inductance. In the second attack, an overproduction threat model is proposed, which significantly decreases the number of measurements needed to reveal the secret key from exponential to linear scale. As a case study, a 4-to-2 priority encoder optimized for SFQ applications is designed and logic locked. The proposed attack is performed on this locked design. Finally, potential countermeasures for each attack type are discussed with the corresponding tradeoffs.

A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications

In this work, an ascendable low power 64-bit priority encoder is designed using a two-directional array to three-directional array conversion, and Split-logic technique and 6-bit is obtained as the output. By using this method, the high performance priority encoder can be achieved. In the conventional priority encoder, a single bit is set as an input, but for a priority encoder with 3-Darray, every input are specified in the matrix form. The I-bit input file is split hooked on M × N bits, similar to 2-D Matrix. In priority encoder with 3-Darray, three directional output comes out, unlike traditional priority encoder, where the output is received from one direction. The development can be achieved by implementing the two-directional array to three-directional array technique. Simulation results show that the proposed 2-D and 3-D priority encoder consumes 0.087039mW and 0.184014mW which is less when compared with the conventional priority encoder. The priority encoders are simulated and synthesized using VHDL in Xilinx Vivado version 2019.2 and the Oasys synthesis tool.

Low power design methodology in quantum-dot cellular automata

The signal distribution network (SDN) in VLSI (Very Large Scale Integration) technology consumes enormous power and layout area among different components. In this article, an extensive focus has been given to designing low-power interconnection in QCA technology. Revolving door elimination techniques, a new crossover methodology, and a circuit without fixed polarized cells are proposed in this research work to make an energy-efficient QCA circuit. The revolving door elimination technique provides us almost 50% energy efficiency over the standard crossover technique. The proposed signal distribution network (SDN) methodology encountered 47% area and nearly 15% energy benefits concerning previously reported SDN techniques. New methodologies are implemented on different nano-communication and computing circuits like XOR gate, odd-even parity generator, priority encoder, decoder, pseudo-random number generator (PRNG) to verify the functionality of proposed methodologies.

High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

SummaryHardware implementation of dedicated arithmetic modules is inevitable for any signal processing system development and computational complexity of such modules could be significantly reduced with improved performance by utilizing Vedic algorithms. Five novel Vedic arithmetic modules for multiplication, square, cube, square root, and cube root are implemented on Zedboard Zynq‐7000 FPGA. A novel 4:2 compressor that uses only primitive gates in critical path is proposed to reduce partial products in the Urdhwa Tiryakhbhyam parallel multiplier achieving the best performance reported so far. Elimination of recursiveness in Antyayordashekepi‐Dwanda squarer results in reduced area while modified Dwanda squarer results in reduced delay. Anurupyena cubic module with 4:2 and 5:2 compressors is implemented from which the one with 4:2 compressor provides the least delay with more than 50% reduction with respect to that of reported cube modules. Modified Vargamula square root and modified cube root modules are also implemented incorporating pipelining, priority encoder, and padding of zero's to achieve better performance. In addition to the delay, in terms of area occupancy, power, and energy consumed (power‐delay‐product), better or comparable performance is also achieved by all the above‐mentioned modules implemented. The dedicated multiplier is used in a 64‐point FFT Implementation and results similar to existing structures are obtained.

Design and comparative analysis of memristor-based transistor-less combinational logic circuits

ABSTRACT Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices.

Correction to: Analysis of all-optical priority encoder using plasmonics waveguide

Correction to: Analysis of all-optical priority encoder using plasmonics waveguide