Design and comparative analysis of memristor-based transistor-less combinational logic circuits

Abstract

ABSTRACT Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices.