4 - Combinational logic design

Abstract

This chapter discusses combinational logic circuit design. A combinational logic circuit consists of a rectangular block containing logic gates only and to which the input signals I1, I2, …., In and from which the output signals O1, O2, …. Om are either logical 0 or 1. Each output is a function of some or all of the input variables. If it is assumed that all the logic gates used in this combinational logic circuit are without time delay, then the outputs (O1, O2, ….…., Om) will appear on their respective output terminals at the same instant as the input signals are applied at the input terminals. One of the simplest combinational logic circuits is the half-adder, which is used for adding together the two least significant digits in a binary sum. There are four possible combinations of two binary digits A and B that can be added together. The chapter illustrates full-adder combinational circuit. When adding any pair of digits other than the two least significant digits, a full adder is required. There are three inputs to a full-adder circuit, these are the two binary digits A and B and an input carry digit Cin from the previous stage. The circuit has two outputs, the sum S and the carry-out to the next most significant stage of the addition, Cout. The carry equation is plotted on the Karnaugh map. If complement arithmetic is used, then an adder circuit can be used for both addition and subtraction and because this leads to an economy of hardware, it is normal practice to use complement arithmetic when performing arithmetic processes in digital machines.