High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

Abstract

SummaryHardware implementation of dedicated arithmetic modules is inevitable for any signal processing system development and computational complexity of such modules could be significantly reduced with improved performance by utilizing Vedic algorithms. Five novel Vedic arithmetic modules for multiplication, square, cube, square root, and cube root are implemented on Zedboard Zynq‐7000 FPGA. A novel 4:2 compressor that uses only primitive gates in critical path is proposed to reduce partial products in the Urdhwa Tiryakhbhyam parallel multiplier achieving the best performance reported so far. Elimination of recursiveness in Antyayordashekepi‐Dwanda squarer results in reduced area while modified Dwanda squarer results in reduced delay. Anurupyena cubic module with 4:2 and 5:2 compressors is implemented from which the one with 4:2 compressor provides the least delay with more than 50% reduction with respect to that of reported cube modules. Modified Vargamula square root and modified cube root modules are also implemented incorporating pipelining, priority encoder, and padding of zero's to achieve better performance. In addition to the delay, in terms of area occupancy, power, and energy consumed (power‐delay‐product), better or comparable performance is also achieved by all the above‐mentioned modules implemented. The dedicated multiplier is used in a 64‐point FFT Implementation and results similar to existing structures are obtained.