Power Supply Rejection Ratio Research Articles

A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency

A dual-rail hybrid analog/digital low-dropout regulator (DRLDO) targeting heterogeneous integration in a multichip package (MCP) platform is presented. Different from the classic single-input-single-output low-dropout regulator (LDO) topology, which incurs an efficiency penalty due to a large dropout voltage, this DRLDO architecture breaks the tradeoff of power-supply rejection and high efficiency by exploiting two rails available in a typical MCP system on a chip. One rail is the larger dropout ac branch rail which helps with power-supply rejection while the other is the low-dropout dc branch that helps with maximizing efficiency. The hybrid combination of analog and digital branches achieves both high efficiency and high power-supply rejection ratio (PSRR) simultaneously. Moreover, a dynamic current steering mechanism actively regulates the current contribution between the two rails and flexibly tunes the PSRR and power conversion efficiency performances. Measurements on a 22-nm CMOS chip demonstrate up to -46-dB PSRR and 89% efficiency across a 0-80-mA load from 1.8-V HV and 1.05-V LV dual-input rails. It improves the efficiency of the conventional analog LDO (ALDO) in MCP applications up to 32% while still maintaining -20-dB PSRR performance.

Design of a Low Temperature Drift Bandgap Reference Circuit with Second-order Curvature Compensation

In order to improve the accuracy and stability of bandgap reference output voltage, a bandgap reference circuit with high power supply rejection ratio and low temperature drift is designed based on 0.18um BCD technology. Based on the traditional bandgap voltage reference structure, this paper designs a current mirror cascade and a prereference circuit to supply power to the bandgap reference, and achieves a high power rejection ratio. At the same time, a PTAT2 current generation circuit is designed to realize the second-order temperature compensation of the reference output voltage. The simulation results show that the power supply voltage is 5V, PSRR is - 80dB, the temperature changes from - 55°C to 125°C, and the reference voltage temperature coefficient is 4.27ppm /°C. The circuit is simple in structure and easy to integrate. It can be widely used in bandgap reference circuit design.

A CMOS RF BeiDou-1 Transceiver for Regional Positioning and Short Message Service Applications

This paper presents a fully integrated CMOS radio-frequency (RF) transceiver for BeiDou-1, a radio determination satellite service system which can provide regional positioning and short message service. The proposed transceiver incorporates a low-IF receiver and a BPSK transmitter to realize a dual-way communication between users and the central control station via satellites. The receiver (RX) RF front-end down-converts the 2491.75 MHz RF signals to a 12.24 MHz IF band with a bandwidth of 8.16 MHz. The complex band-pass filter utilizes passive compensation technique to compensate the phase lag and achieve in-band flatness. The 4.08 Mchip/s baseband signal alternatively selects one of the differential 1615.68 MHz local signals to achieve BPSK modulation for the transmitter (TX). Besides, on-chip low dropout regulators adopt improved power supply rejection ratio techniques by integrating active filtering to obtain stable 1.5 V supply voltages. The transceiver is fabricated in a 130 nm CMOS technology and occupies an area of 5.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with electrostatic discharge circuitry and pads included. The RX channel achieves a 106 dB maximum voltage gain with a 65 dB dynamic range, a 4.95 dB noise figure and a 46 dB image rejection ratio. The output power for the TX ranges from -10 dBm to 5 dBm, with a phase error less than 1.5 degree.

An integrated microelectrode array system for neural signals recording

A CMOS neural signal recording microelectrode array system integrated with signal processing circuits is proposed in this work. A model of the electrode-neuron interface is built. Analytic derivation and simulation results reveal some interesting phenomena and provide a theoretical basis for the design of the Micro-Electrodes Array (MEA) which is a crucial direction for optimizing MEA and improving Signal-to-Noise Ratio (SNR). The new Operational Trans-conductance Amplifier (OTA) utilizes a Flipped Voltage Follower (FVF) topology to effectively decrease the power supply voltage and power consumption while still keeping the gain, Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR) at a high value and the noise at a low level. Using the active low-frequency suppression instrumentation amplification technique, the proposed system topology ameliorates the disadvantage of the conventional capacitive coupling structure which occupies a large area. An 8-channel prototype was fabricated in a 0.5 μm standard CMOS process, occupying 5 × 5 mm2. The prototype OTA consumes less than 3 μW, providing 11.9 μVrms input referred noise with 83.9 dB CMRR and 99.4 dB PSRR, which providing an effective method for in vitro neural studies.

Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

Designing programmable current-mode Gaussian and bell-shaped membership function

In this paper, a procedure is proposed to implement a novel and effective Gaussian-shaped and Bell-shaped membership function. The circuit is designed in a current mode. Therefore, the power consumption has been decreased. Higher power supply rejection ratio is also achieved by the use of a differential structure. The most important aims are to design simple, accurate and low power consumption circuits. The proposed circuit operates in the saturation region. Therefore, high-accuracy, as well as the high-speed performance and independency to the temperature variations, are obtained. Programmability, power consumption and parameters variations of the proposed circuit are also presented. The simulations are done in 0.18 µm CMOS technology.

A 0.5-V Capless LDO With 30-dB PSRR at 10-kHz Using a Lightweight Local Generated Supply

An analog low dropout regulator (LDO) that can operate at ultra-low voltage (ULV) with high power supply rejection ratio (PSRR) is presented in this brief. The supplies of the error amplifier and the power stage in this LDO are separated, and a lightweight local generated supply (LLGS) is proposed to guarantee the proper function of the associated error amplifier in ULV mode. This LLGS assisted analog LDO has been experimentally verified in 0.13 μm CMOS technology and it only occupies an active area of 0.035 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results indicate that this LDO can achieve greater than 30 dB PSRR up to 10 kHz at supply voltage as low as 0.5 V.

A special technique for Recycling Folded Cascode OTA to improve DC gain, bandwidth, CMRR and PSRR in 90 nm CMOS process

Abstract Design and simulation of an improved recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The new idea is based on minor changes in the conventional structure. Our improved amplifier is capable to enhance DC gain and unity gain bandwidth (UGBW) in the same −3dB frequency as for RFC structure. Moreover, fast-settling time, input-referred noise, total harmonic distortion (THD) and performances of power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) are also improved. Simulation results in 90 nm CMOS process indicate that the proposed amplifier has about 2 times the unity gain bandwidth (360 versus 175 MHz) and also has twice gain boosting (68.6 versus 62.5 dB) in the same −3 dB frequency and capacitor load of 10 pF @1.2 V power supply. The results also demonstrate a good figure of merit (FOM), and low sensitivity of temperature and power supply variations for the proposed amplifier.

A high PSRR bandgap voltage reference with piecewise compensation

This paper describes an alternative high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) circuit with piecewise compensation. A proportional to absolute temperature (PTAT) current structure with high loop gain is adopted to achieve high PSRR, a current proportional to absolute temperature square (PTAT2) circuit is used to implement the temperature piecewise compensate. Experimental results of the proposed BGR implemented in a 0.5 ​μm CMOS process demonstrate that a PSRR of 83 ​dB is achieved, and a temperature coefficient (TC) of 8.83 ​ppm/°C over a temperature range of 165 ​°C (−40 ​°C–125 ​°C) is realized.

An Output Capacitorless Low-Dropout Regulator With a Low-VDD Inverting Buffer for the Mobile Application

To provide power to the latest mobile applications that use functions with heavy loads, in this letter, we present a capacitorless low-dropout regulator (LDO) that supplies a large load current up to 600 mA. The proposed buffer and the feedforward paths are used to provide a stable operation and fast response along with a large load current. Owing to these schemes, the proposed LDO has a high unity gain frequency of 2.85 MHz at 100 mA with a total compensation capacitance of 5.1 pF. In addition, the LDO operates under a wide input voltage range of 1.5–5.0 V owing to the low-VDD structure. Also, a power supply rejection ratio was –52 dB at 100 kHz. The chip was implemented with a small size of 0.082 mm2 using the I/O devices of a 0.18 μ m CMOS process with a minimum length of 0.5 μ m.

Adjustable Output CMOS Voltage Reference Design

In this brief, a CMOS voltage reference based on mutual temperature compensation using NMOS transistors of the same threshold type is advanced. The technique consists in subtracting two voltages that present similar complementary-to-absolute-temperature (CTAT) behavior, which are appropriately generated from the same threshold-type NMOS transistors operating as diodes in different inversion levels. The proposed topology provides an adjustable voltage and avoids the use of start-up drivers. The circuit design was carried out in a 180 nm CMOS process. Experimental results verified the effectiveness of the presented technique, and produced a reference voltage of 500 mV. The circuit operates with a supply voltage ranging from 1.2 V to 1.8 V, consumes $4.7~\mu \text{A}$ at 27 °C, has a temperature coefficient (TC) of 22 ppm/°C from 0 °C to 100 °C, and presents a power supply rejection ratio (PSRR) of −42 dB.

Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach

This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for start-up circuit. The measured settling time for output reference voltage is observed to be less than 4 μs. No filtering capacitor is used to improve the PSRR, which is –97 dB up to 1 MHz and subsequently reduces to –47.5 dB at 158 MHz.

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

Design of a sub-1V CMOS reference voltage generator

In this paper a low complexity, sub-1V, reference voltage generator with low voltage sensitivity over PVT variation and high power supply rejection ratio (PSRR) is proposed. It consists of a traditional bandgap reference core where resistors are used for generating both the PTAT and CTAT currents, which are then added forming a temperature-independent current. A new 1 V modified folded cascode operational amplifier is proposed and used in the main bandgap’s loop resulting in low offset, high loop gain and adequate loop phase margin of 58.9°. The loop consists of only two inverting stages and the circuit can be integrated entirely without the need of external large capacitors for frequency compensation. A regulated cascode current source is employed for accurately mirroring of the core temperature-independent current to a resistive load, where the reference voltage is generated. The proposed circuit was simulated in SPECTRE achieving an output reference voltage variation of 3.62%, without trimming, over process variation corners with ±10% variation of the 1 V power supply voltage and within the industrial temperature range, from −40 °C to 125 °C. The temperature coefficient from −40 °C to 125 °C is 6.81 ppm/°C at 1 V at the typical process corner. The PSRR at 1 Hz and the output RMS noise within a bandwidth of 100 MHz are −69.85 dB and 279 μV RMS, respectively, at the typical process corner, at a supply voltage of 1 V and temperature of 27 °C. Typical power consumption is 452 μA at 1 V.

A sub-1V high PSRR OpAmp based β-multiplier CMOS bandgap voltage reference with resistive division

&lt;span lang="EN-US"&gt;A sub-1V opamp based β-multiplier CMOS bandgap voltage reference (BGVR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed in this paper. A current mode regulator scheme is inserted to isolate the supply voltage of the operational amplifier (opamp) and the supply voltage of the BGVR core from the supply voltage source in order to reduce ripple sensitivity and to achieve a high PSRR. The proposed circuit is designed and simulated in 0.18-μm standard CMOS technology. The proposed voltage reference delivers an output voltage of 634.6mV at 27°C. Tthe measurement temperature coefficient is 22,3ppm/°C over temperature range -40°C to 140°C, power supply rejection ratio is -93dB at 10kHz and -71dB at 1MHz and a line regulation of 104μV/V is achieved over supply voltage range 1.2V to 1.8V. The layout area of the proposed circuit is 0.0337mm&lt;sup&gt;2&lt;/sup&gt;. The proposed sub-1V bandgap voltage reference can be used as an internal voltage reference in low power LDO regulators and switching regulators.&lt;/span&gt;

A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications

A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit $\Sigma \Delta $ ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44- $\mu ~V_{\mathbf {rms}}$ noise performance. The MCIA occupies only 0.3 mm2 and consumes 60 $\mu \text{W}$ for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology.

Highly Digital Second-Order $\Delta\Sigma$ VCO ADC

A continuous-time second-order $\Delta \Sigma $ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.