An integrated microelectrode array system for neural signals recording

Abstract

A CMOS neural signal recording microelectrode array system integrated with signal processing circuits is proposed in this work. A model of the electrode-neuron interface is built. Analytic derivation and simulation results reveal some interesting phenomena and provide a theoretical basis for the design of the Micro-Electrodes Array (MEA) which is a crucial direction for optimizing MEA and improving Signal-to-Noise Ratio (SNR). The new Operational Trans-conductance Amplifier (OTA) utilizes a Flipped Voltage Follower (FVF) topology to effectively decrease the power supply voltage and power consumption while still keeping the gain, Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR) at a high value and the noise at a low level. Using the active low-frequency suppression instrumentation amplification technique, the proposed system topology ameliorates the disadvantage of the conventional capacitive coupling structure which occupies a large area. An 8-channel prototype was fabricated in a 0.5 μm standard CMOS process, occupying 5 × 5 mm2. The prototype OTA consumes less than 3 μW, providing 11.9 μVrms input referred noise with 83.9 dB CMRR and 99.4 dB PSRR, which providing an effective method for in vitro neural studies.