A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency

Abstract

A dual-rail hybrid analog/digital low-dropout regulator (DRLDO) targeting heterogeneous integration in a multichip package (MCP) platform is presented. Different from the classic single-input-single-output low-dropout regulator (LDO) topology, which incurs an efficiency penalty due to a large dropout voltage, this DRLDO architecture breaks the tradeoff of power-supply rejection and high efficiency by exploiting two rails available in a typical MCP system on a chip. One rail is the larger dropout ac branch rail which helps with power-supply rejection while the other is the low-dropout dc branch that helps with maximizing efficiency. The hybrid combination of analog and digital branches achieves both high efficiency and high power-supply rejection ratio (PSRR) simultaneously. Moreover, a dynamic current steering mechanism actively regulates the current contribution between the two rails and flexibly tunes the PSRR and power conversion efficiency performances. Measurements on a 22-nm CMOS chip demonstrate up to -46-dB PSRR and 89% efficiency across a 0-80-mA load from 1.8-V HV and 1.05-V LV dual-input rails. It improves the efficiency of the conventional analog LDO (ALDO) in MCP applications up to 32% while still maintaining -20-dB PSRR performance.