Abstract
A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.
Highlights
The Internet of Things (IoT) has played a significant role in many aspects of modern life, such as medical care, automobiles, homes, and amenities [1]
The chopper stabilization technique reduces baseband noise through up-modulating the flicker noise and DC offset in the baseband; a thermal-noise-limited level can be achieved
To attenuate the flicker noise and DC offset in the baseband, the chopper stabilization technique is employed
Summary
The Internet of Things (IoT) has played a significant role in many aspects of modern life, such as medical care, automobiles, homes, and amenities [1]. The need for smaller, less expensive high-performance sensors has developed in a way that makes sensors and sensing elements smaller To readout these sensors precisely, readout circuits should have low-noise, high input impedance, low power, and high common-mode rejection ratio (CMRR). Up-modulated DC offset and flicker noise can cause a ripple in the output To solve this problem, a ripple reduction loop (RRL) is used to demodulate the ripple and provide negative feedback to the input through the integrator [13]. A multipath topology is employed to compensate for the notches of the transfer function in the chopping frequency band This CFIA achieves a high CMRR, high input impedance, and low power consumption
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