Power Supply Noise Research Articles

Characterization of the Power Distribution Network for Commercialized STM32s Using a Resonance Frequency Measurement Method

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints on the design of the power distribution network (PDN), which directly impacts power supply noise. Therefore, characterizing the PDN is necessary. This paper introduces a cost-effective measurement and modeling method to estimate the die-package resonance frequency of the PDN, a major threat to power integrity. The method, applied to two 32-bit MCUs from STMicroelectronics with varying PDN configurations, enables the identification of the die-package resonance frequency. The results lead to the refinement of the die capacitance model for both cases, with a maximum relative error of less than 7%. The final objective is to implement the measurement system in the die in order to adjust the PDN if necessary.

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

Detector diode circuit noise measurement and power supply method selection for the fiber optic seismograph

Detector diode circuit noise measurement and power supply method selection for the fiber optic seismograph

Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.

A Methodology for Predicting Acoustic Noise From Singing Capacitors in Mobile Devices

Multilayer ceramic capacitors (MLCCs) connected to a power distribution network (PDN) can create acoustic noise through a combination of the power rail noise at the MLCCs and the piezoelectric effect of the capacitor's ceramic material. The deformation of the MLCCs brought on by power supply noise creates vibrations which cause the printed circuit board (PCB) to vibrate and generate the audible acoustic noise. In the following paper, a simulation methodology is presented to analyze the acoustic noise created by MLCCs on a PCB. A simulation model for the PCB vibration modal response is built and the modal superposition method is used to analyze the harmonic response of the PCB excited by the capacitor. By multiplying the measured power noise spectrum on the MLCC with the simulated deformation of the PCB found from the harmonic response analysis, the total response is obtained. Simulated results show a good correlation with the measured acoustic noise. The proposed method shows promise for analyzing and predicting the acoustic noise from singing capacitors.

A Low-Voltage Class-D VCO with Implicit Common-Mode Resonator Implemented in 55 nm CMOS Technology

This paper presents a Class-D voltage-controlled oscillator (VCO) with a hybrid switch capacitor array. In order to reduce the phase noise of the oscillator, an implicit common-mode resonance technique is used, effectively suppressing the conversion of power supply noise to VCO phase noise. At the same time, due to the use of a transformer in implicit common-mode resonance technology, the core area of the oscillator is not significantly increased compared with the traditional Class-D VCO. Based on the proposed technology, the proposed VCO exhibits lower phase noise compared to the original Class-D VCO, and also has many different advantages compared to low-voltage VCOs produced by similar technological processes. The proposed VCO was designed in a 55 nm CMOS process. Simulation results show that this VCO has an operating range from 4.36 to 6.43 GHz, resulting in the frequency tuning range (FTR) of 38.5%. In addition, its power consumption was 3.46 mW, the phase noise at 4.36 GHz was −124.2 dBc/Hz@1 MHz, and the figure of merit (FoM) was −191.6 dBc/Hz@1 MHz. The core area is 0.15 mm2.

Development of Knowledge-Based Artificial Neural Networks for Analysis of PSIJ in CMOS Inverter Circuits

In this article, a knowledge-based artificial neural network (ANN) is developed for predicting jitter in CMOS inverter circuits in the presence of power supply noise (PSN). The proposed ANN provides for efficient training in a hybrid approach using input data extracted from both analytical closed-form expressions and a circuit simulator. The proposed ANN demonstrates a reasonably accurate prediction of power supply-induced jitter (PSIJ) with results that closely match that from directly using a circuit simulator (HSPICE) for a case study with 22-nm CMOS technology.

1-b Delta-Sigma ADC-Based Power Side-Channel Attack Detection Sensor

Countermeasures against power side-channel attack (SCA) range from algorithmic modifications to modifying the power consumption characteristics of the device by the inclusion of noise sources or suppressing the current signature. However, these techniques are, in most cases, passive protection techniques and come with the unacceptable area and power overheads for resource-constrained devices. In this letter, we propose a power SCA detection sensor based on a 1-b delta-sigma analog-to-digital converter, which allows for detection of an ongoing attack within as fast as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$6.4\,\mu \text{s}$</tex-math></inline-formula> , with immunity to power supply noise, at an area overhead of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\leq 8\%$</tex-math></inline-formula> for advanced encryption standard (AES)-256, while reducing the power overhead by 66% compared to the current state-of-the-art.

A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments

A frequency tunable phase-locked loop (PLL) applied in high energy particle detector has been developed. In order to achieve high detection efficiency, high requirements are promoted for on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An LC voltage-controlled oscillator (LC-VCO) is used to generate the local clock. A third-order MASH sigma-delta (Σ - Δ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. In order to further reduce the phase noise, pre-set and post-set binary frequency dividers are employed. In the prototype chip a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180 nm CMOS process. It costs an area of 1.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power of 8.1 mW at a 1.8 V power supply. The measured output frequency range is 400 - 530 MHz with the reference frequency of 25 - 35 MHz. The RMS jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than -61 dBc, and the phase noise at 1 MHz frequency offset is less than -113 dBc/Hz.

Analytical Modeling of Deterministic Jitter in CMOS Inverters

With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g. jitter, cross-talk, electromagnetic interference etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of Power Supply Noise (PSN), Data Noise (DN), and Ground-Bounce Noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE based simulator as well as doing the same with the experimental results using two different CMOS inverter Integrated Circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation (UMC). Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the EDA tool and the experiments.

Precision Design and Fabrication of Noise-free High-Frequency Amplifier Board for Enhanced Signal Processing

An optical signal processing system is widely used for long-distance signal transmission with high speed and low attenuation. It plays a fundamental role in optical communication systems that involves transmitting, receiving, amplifying, and manipulating optical signals which are high-frequency signals. This paper portrays the design of a high-frequency amplifier to amplify the low-amplitude high-frequency, electrical signal procured from the optical signal. A four-stage high frequency amplifier has been designed using an AD8009 high-frequency Op-amp for the highest frequency of 1GHz, and for the fastest rise time of 0.35 nanoseconds. This amplifier board incorporates the high-frequency PCB design rules related to the characteristic impedance, impedance matching, signal crosstalk, the propagation delay of the transmission lines, transmission techniques for the ground plane, and termination of transmission lines for the effective use of high-frequency signals. It has also counted on the issues of electromagnetic interference, power supply decoupling, noise, and high-speed operational amplifier. The proposed system resulted in suitable amplification of low amplitude high-frequency electrical signal, having no signal cross-talks, electromagnetic interference, signal ringing, signal reflections, and posed larger bandwidth. The improved quality of high frequency processed signals with good signal integrity and moderate circuit oscillations achieved by this system will benefit the optical communication system.

On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies

ABSTRACT In several instances, the electronic appliances used in the Internet-on-Things (IoT) systems fail to perform according to their full capability. One of the main reasons pertaining to this issue is the IoT devices are usually controlled by clock-driven application-specific processors enabling them to communicate over the common network and accomplish given tasks. But these processor chips are mostly prone to supply noise and adversely affect the performance of the IoT systems. In this article, the problem of on-chip power supply noise (PSN) is discussed and how clock gating (CG) is a potential candidate to mitigate i ( t ) and d i ( t ) d t which are the dominant factors of instigating the overall on-chip PSN. Majority of the CG schemes are examined and it is seen that LCT-CG implementation can potentially commit 84.44% less PSN compared to the non-gated peer as well as 55.21%, 54.45% and 74.47% lesser than the other CG schemes like LB-CG, NC2MOS-CG and DG-CG, respectively. In addition, it is also observed that with the inclusion of LCT-CG in IBM® i650 A-Z80 processor chip, the system lifetime is improved by 17.70% compared to the non-gated peer. In addition, the industry standard of implementing CG schemes in integrated circuit (IC) chips is reviewed and it is found quite different from the traditional methods. Therefore, an extensive study is performed to portray the possibility of LCT-CG can become an industry standard in the forthcoming days.

Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

SEMG-based technology for silent voice recognition

Silent speech recognition (SSR) is a system that implements speech communication when a sound signal is not available using surface electromyography (sEMG)-based speech recognition. Researchers have used surface electrodes to record the electrically-activated potential of human articulation muscles to recognize speech content. SSR can be used for pilot-assisted speech recognition, communication of individuals with speech impairment, private communication, and other fields. In this feasibility study, we collected sEMG data for ten single Mandarin numeric words. After reducing power frequency interference and power supply noise from the sEMG signal, short-term energy (STE) was used for voice activity detection (VAD). The power spectrum features were extracted and fed into the classifier for final identification results. We used the Hold-out method to divide the data into training and test sets on a 7-3 scale, with an average accuracy of 92.3% and a maximum of 100% using a support vector machine (SVM) classifier. Experimental results showed that the proposed method has development potential, and is effective in identifying isolated words from the sEMG signal of the articulation muscles.

New negative‐grounded capacitance multiplier circuits

SummaryIn this communication, three new negative‐grounded capacitance multiplier (NGCM) circuits employing a single current feedback operational amplifier (CFOA), two resistors, and a grounded capacitor (which is most suitable for parasitic absorption and also IC implementation point of view) are investigated. No matching constraints are required for any of the proposed circuit realizations. Out of the three proposed circuits, multiplication factor of one of the capacitance multiplier can be controlled electronically as the controlling resistor is grounded, which can easily be replaced by a voltage‐controlled resistor (VCR). Error analysis of the proposed NGCMs has been carried out, and the results have been compared with those obtained from ideal analysis. To substantiate the feasibility of the proposed circuits, macro model of CFOA has been used, and the simulations have been performed in Personal Simulation Program with Integrated Circuit Emphasis (PSPICE). Simulation results for frequency analysis, Monte‐Carlo analysis, and temperature analysis have been included for the theoretical justification. Noise analysis and power supply rejection ratio analysis have also been carried out for the proposed circuits. The multiplication factors of the proposed NGCMs have been obtained up to a maximum value of 2001. The impedance and phase of the proposed NGCM structures are insensitive with temperature. The functionality of the proposed structures has also been validated experimentally using commercially available IC AD844‐type CFOA.

Reduction of noise induced by power supply lines using phase-locked loop

An experimental implementation for the reduction of power-line noise in delicate signal detection is presented. This implementation improves the signal-to-noise ratio without limiting the bandwidth of the measurement. A sinusoidal wave and its harmonics, both synchronized with the frequency of the power line, are used to cancel out the power supply noise induced in the measurement signal. The wave and the harmonics are generated via a phase-locked loop implementation. Their amplitude and phase are adjusted, and then they are added to the measurement signal using a series of operational amplifiers to compensate for the noise. Although we applied this method to the particular case of scanning tunneling microscopy measurements, considerably improving the image quality, our implementation can be applied to other measurement systems for which noise from the power lines can compromise the signal detection.

Experimental investigation into the aerodynamic and aeroacoustic performance of bioinspired small-scale propeller planforms

The multi-rotors have a limited operational period and generate too much noise, which is insufficient for complex tasks and adversely affects humans’ and animals’ health. Nevertheless, their market has become increasingly popular. Therefore, low-noise products are more competitive, and aerodynamic and acoustic improvements are critical. This investigation aims to design a small bioinspired propeller with the same power input as a conventional propeller to achieve the same or better aerodynamic performance while decreasing noise. Accordingly, an experiment investigated the impacts of operation conditions and varied geometric parameters on six small propellers' aeroacoustic performances with a unique planform shape inspired by five insects and one plant seed, such as Blattodea, Hemiptera, Hymenoptera, Neuroptera, Odonata, and maple seed. Each propeller was operated at eleven rotational speeds ranging from 3000 to 8000 RPM with no freestream velocity for simulating hover conditions. Compared to the baseline propeller, the results demonstrate that all bioinspired propellers produce more thrust for the same power supply, reduce harmonic and broadband noise, and provide a better noise level. Also, their rotational speed is lower and their figure of merit is higher than the baseline propeller at hover flight with 3N thrust. They all outperform the baseline propeller in terms of hover efficiency at all thrust values considered. Besides, the Neuroptera propeller is more efficient than other propellers, decreasing 5.5 W of power and reducing 7.9 dBA at hover flight with 3N thrust and 1.5 meters distance, compared to the baseline propeller.

A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Buried power rail (BPR) and back-side power delivery grid have been proposed as solutions to scaling challenges that arise beyond the 5-nm technology node, mainly to lower IR drop and further shrink area. This article demonstrates a holistic evaluation of this technology and its variants at the microprocessor level. This is carried out by taking an Arm Cortex-A53 design through the standard-VLSI physical design implementation flow on Imec’s iN6 node, equivalent to the industry 3-nm technology node, which features the buried power technology. The power, performance, area, on-chip IR drop, and off-chip voltage droop metrics are benchmarked, and implications on power gating are explored. An extensive Design-Technology-Co-Optimization (DTCO) study of the back-side power grid is presented to enhance the decoupling capacitance by sweeping associated technology parameters showcasing further optimization opportunities in manufacturing. The conclusions of this work highlight that the front-side (FS) power delivery network (PDN) with buried rails achieves a 25% lower on-chip IR drop and 17% lower off-chip voltage droop (power supply noise) resulting in 21% lower guard band voltage. On the other hand, the back-side power grid with BPRs achieves 85% lower on-chip IR drop and 30% off-chip voltage droop resulting in 60% lower guard band voltage. In addition, the impact of BPRs, and back-side power grids on power gated designs are evaluated.

Wide band differential on-chip monitoring of system on chip power supplies noise

Differential high-speed sensors are addressed on the real time on chip monitoring of system on chip power supply noise. The state-of-the-art topologies are addressed thoroughly in relation to their capability on capturing wireless communications products noisy signals with frequency content from low MHz to several GHz, and with amplitudes in the range of tens of mV. A design methodology on wideband RFCMOS sensor design, and a respective sensor are proposed. The sensor is implemented in a 65 nm RFCMOS process, provides 20 GHz bandwidth, 6.55 dB amplification and 100 mV 1 dB compression point. This sensor is benchmarked versus all the respective differential sensors, designed and simulated also in the same process, and stretched as to reach the highest possible bandwidth. Its unique speed capabilities are based on use of cascaded high gain-bandwidth CMOS inverters in a Cherry Hooper topology with feedforward cancellation. Its performance imposes this architecture and the methodology beneath, as the most advanced technique on capturing supply noise on wireless communications system on chip.

Design and Distortion Analysis of a Power Delivery Network in the Presence of Internal Supply Noise

This article presents a novel relationship between the duty cycle and power supply noise (PSN) for a feedback control circuit of a dc–dc buck converter. The derived relation is equally valid for the other high-speed circuits. Based on the derived relation, the closed-form expressions of the harmonics quantities for the dc–dc buck converter (including feedback circuitry) and power delivery network (PDN) are developed. The derived expressions of the distortions include the effect of small variations at the power supply and input dc terminals. A combination of two techniques, the Volterra series and the estimation-by-inspection methods, are used to derive the nonlinear quantities. The estimation-by-inspection method is used to model the feedback circuit, including the effects of PSN. The Volterra series derive the nonlinear quantities of the converter. The analytical results are compared with the simulation results for both the examples (designed in 180-nm LDMOS technology) in terms of mean percentage error (MPE) and computational (CPU) time.