A Frequency-Tunable Fractional-N PLL for High-Energy Physics Experiments

Abstract

A frequency tunable phase-locked loop (PLL) applied in high energy particle detector has been developed. In order to achieve high detection efficiency, high requirements are promoted for on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An LC voltage-controlled oscillator (LC-VCO) is used to generate the local clock. A third-order MASH sigma-delta (Σ - Δ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. In order to further reduce the phase noise, pre-set and post-set binary frequency dividers are employed. In the prototype chip a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180 nm CMOS process. It costs an area of 1.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power of 8.1 mW at a 1.8 V power supply. The measured output frequency range is 400 - 530 MHz with the reference frequency of 25 - 35 MHz. The RMS jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than -61 dBc, and the phase noise at 1 MHz frequency offset is less than -113 dBc/Hz.