Power Supply Noise Research Articles

High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads

A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The proposed LDO does not require an external capacitor making it suitable for System-on-Chip (SoC) applications. The low-frequency PSR of the LDO varies with load current as the transconductance and output conductance of the power transistor depend on the load current. The proposed LDO is capable of maintaining a constant and high PSR for varying loads by using an adaptive network. The NMOS pass transistor in the adaptive network tracks the power-supply noise through the power transistor and bypasses this noise current through it to the ground. This helps to avoid the flow of this noise current through the load and thus the circuit can achieve high and constant PSR for varying loads. The LDO with adaptive network achieves very high power-supply rejections of [Formula: see text][Formula: see text]dB at low frequencies and [Formula: see text][Formula: see text]dB at 1[Formula: see text]MHz, for a load current of 4[Formula: see text]mA. This LDO is implemented in 0.18-[Formula: see text]m CMOS technology and consumes 1.35-mW quiescent power over the range of 1–10[Formula: see text]mA of the load current.

Study on the Effect of Switching Power Supply Noise and EFT / B Noise on the Load Side

Study on the Effect of Switching Power Supply Noise and EFT / B Noise on the Load Side

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation

This article presents a noise-shaping time-to-digital converter (TDC) based on an inverted ring oscillator (IRO). By inverting the oscillation direction, the proposed IRO-TDC achieves quantization error and mismatch noise shaping, in-band noise reduction, coherent noise cancellation, and low disturbance to power supply at the same time. A noise model is proposed to analyze the noise performance of the proposed TDC, and to compare its noise with TDCs based on gated ring oscillator (GRO) and switched ring oscillator (SRO). An IRO-TDC prototype is fabricated in a 65 nm CMOS technology to verify the proposed IRO technique and noise model. With a sampling rate of 200 MS/s, the TDC achieves an integrated noise of 196 fsrms in a 3 MHz bandwidth with a constant power dissipation of 13.2 mW. The measured coherent noise cancellation ratio is up to 36.4 dB. To the best of our knowledge, this is the first demonstration of an oscillator utilizing oscillation inversion for noise reduction and coherent cancellation to protect the TDC from power supply noise, ground noise, and substrate noise. Due to its noise cancellation and low disturbance to power supply, the proposed IRO technique also alleviates the design complexity of power supply in future TDC applications.

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over $3\times $ improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA’s process scalability by comparing the measured results of the DA-based MDAC prototyped in 65- and 28-nm CMOS. We observe $2\times - 3\times $ improvement in speed, power, and area mainly resulting from the DA’s process scalability.

A Cross-Layer Framework for Temporal Power and Supply Noise Prediction

In modern microprocessor and SoC designs, supply noise margin has been significantly reduced due to the continuously decreasing supply voltage level. On the other hand, with increasing current density, chips may see larger supply noise variations on various spots and from time to time. As a result, chip robustness and reliability are inevitably deteriorated with more frequent supply noise emergencies. It is therefore crucial to have an efficient supply noise prediction method to enhance design robustness. The state-of-art solutions either try to build a spatial noise estimation framework at the layout-level using the limited distributed physical noise sensors or attempt to develop emergency predictors at the architecture-level thus ignore back-end power delivery details. In this paper, we propose a cross-layer framework for temporal supply noise prediction. Our method not only accounts for the temporal characteristics of workload execution at micro-architecture-level but also incorporates the power delivery model at the circuit-level into such system-level prediction. In order to enable the capability of on-the-fly noise prediction, we first bridge the gap between system-level workload and micro-architectural-level power by employing an ordinary least square-based power estimation model and an adaptive auto-regressive integrated moving average model (ARIMA)-based power prediction model. Then a layout-level supply noise model is developed to explore the correlations between micro-architectural-level power and layout-level supply noise. Compared with existing methods, the proposed ARIMA-based power model improves the prediction performance by up to 37.5%/63.0% in X86/ARM. Moreover, compared with SPICE simulation, our framework is able to estimate present supply noise with an average error of 0.005% and predict future supply noise with an average error of 1.58%/1.17% for X86/ARM architecture.

Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise

This article addresses the nonlinear behavioral modeling of tunable drivers with preemphasis including power supply noise. The proposed model relies on the use of state-aware weighting functions that control the transitions of the driver’s output stage for the scenarios where switched input logic states are shorter than the preemphasis duration, and the influence of supply voltage variation is considered. For the power supply noise analysis, the method is applied to multiple ports. Feedforward neural networks (FFNNs) are used to implement the state-aware weighting functions, and recurrent neural networks (RNNs) are used to capture the dynamic memory characteristics of driver’s ports. For tunable drivers in the state-of-the-art design covering features such as drive strength and preemphasis, a parameterized model that considers driver control parameters is presented. As a black-box approach, the resulting model protects intellectual property (IP). Practical industrial driver examples demonstrate the good accuracy, flexibility, and significant simulation speedup of the proposed model, which can facilitate the signal and power integrity (SIPI) analysis.

Power Delivery Network Modeling and Benchmarking for Emerging Heterogeneous Integration Technologies

In this article, a power delivery network (PDN) modeling framework for heterogeneous integration platforms is presented, which includes both IR-drop and transient analysis. The model is validated using IBM power grid benchmarks, and maximum relative errors are less than 7.3%. To evaluate interposer and bridge-chip-based integration platforms, we assume a field-programmable gate array (FPGA)-CPU 2.5-D integration platform, of which the FPGA consumes 45 W and the CPU consumes 75 W. The simulation results show that an interposer with dense power/ground grid and microbumps can suppress power supply noise (PSN) by a small margin with the requirement of high-density through-silicon vias (TSVs). For bridge-chip-based integration, under the assumption that the active dice above the bridge-chips are not connected to the package power/ground planes, some PDN challenges are evaluated. Using multiple bridge-chips and smaller overlap areas between the bridge-chips and the active dice, the worst-case PSN in bridge-chip-based integration is minimized. Next, we perform parametric studies for these 2.5-D integration platforms as a function of C4 bump pitch and metal layers. Lastly, we propose to use TSVs in the bridge-chip to reduce PSN. With nine bundled TSVs of $8~\mu \text{m}$ diameter, the IR-drop of bridge-chip-based integration technologies is only 1% higher than the standalone case.

Reduction of Environmental Magnetic Field Noise for Detection of Small Magnetic Contaminants

When performing high-sensitivity magnetic measurements via a high-sensitivity magnetic sensor such as a SQUID (Superconducting QUantum Interference Device) magnetometer, it is necessary to shield from environmental magnetic noise by employing a magnetic shield box. In general, however, the low frequency of such noise decreases the shielding performance of the magnetic shield box. Hence, the magnetic metallic contaminant signal and the low-frequency ambient magnetic field noise overlap, which makes filtering a challenging task. Therefore, we studied a system that suppresses gradient magnetic noise such as low-frequency environmental noise superimposed on a contaminant signal and commercial power supply noise localized spatially.

Controlled emotional tactile stimulation during functional magnetic resonance imaging and electroencephalography

BackgroundTactile stimulation used to induce emotional responses is often not well-controlled. Replicating the same tactile stimulations across studies is difficult, compared to replicating visual and auditory modalities, which have standardized stimulus sets. Standardizing a stimulation method by replicating stimuli across studies is necessary to further elucidate emotional responses in neuroscience research using tactile stimulation. The new methodWe developed a tactile stimulation device. The device's ultrasonic motor and optical force sensor have the following criteria: (1) controls the physical property of stimuli, pressure, and stroking speed; (2) measures actual touch timing; (3) is safe to use in a magnetic resonance imaging (MRI) scanner; and (4) produces low noise in electroencephalography (EEG) and MRI. ResultsThe noise level of the device's drive was sufficiently low. For the EEG experiment, we successfully used signal processing to diminish the commercial power supply noise. For functional MRI (fMRI) scans, we found <5% signal loss occurred during device rotation. Comparison with existing method(s)We found no previous report about the noise level of a tactile stimulation device used to induce emotional responses during EEG and fMRI recordings. The signal loss rate was comparable with that of other robotic devices used in MRI scanners. Emotional feelings induced by this stimulation method were comparable with those elicited in other sensory modalities. ConclusionsThe developed device could be used for cognitive-affective neuroscience research when conducting EEG and fMRI scans. The device should aid in standardizing affective tactile stimulation for research in psychology and cognitive neuroscience.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A Differential Optical Receiver With Monolithic Split-Microring Photodetector

This paper presents a high-sensitivity, fully differential (FD) optical receiver (RX) for high-density system-on-chip applications. The high digital activity prominent in such applications creates common-mode and power-supply noise, which degrades the optical RX sensitivity. To suppress these noise sources and enhance the RX sensitivity, an optical RX is proposed that realizes FD operation by using a new resonant split-microring photodetector. The complete RX is implemented in a 45-nm SOI CMOS with no process changes. When aptly biased, the detector outputs FD photocurrent with $\mu \text{A}_{\mathrm {pp}}$ without reducing the bandwidth or significantly impacting the RX energy efficiency.

VCO-Based ADC With Built-In Supply Noise Immunity Using Injection-Locked Ring Oscillators

Analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs) demonstrate superior hardware efficiency. They benefit from the technology scaling; however, they exhibit inferior performance against supply noise. The objective of this brief is, therefore, to present a VCO-based ADC architecture with built-in immunity against supply noise. The proposed technique exploits the dynamics of injection locking oscillation in multiphase ring topology. It provides a system-level cancelling of power supply noise, independent of the VCO architecture used in the time-mode ADC. The design functionality has been demonstrated using behavioral and transistor-level simulations using 65 nm technology. Under a 10% mismatch of VCO gain and a 128 MS/s data rate, the reported power supply noise rejection improvement is 25 dB, as compared with a typical VCO-based ADC.

A Dual-loop Phase Locked Loop with Frequency to Voltage Converter

This paper proposes a 1.5-GHz ring oscillator-based dual-loop phase locked loop (PLL) with a frequency-to-voltage converter (FVC). By forming an additional high bandwidth path in the conventional PLL with the FVC, the proposed dual-loop PLL can effectively suppress the voltage controlled oscillator (VCO) noise and reference noise. Tested with an arbitrary power supply noise injection, the phase noise of the proposed PLL with FVC was -88.6 dBc/Hz at a 1-MHz offset, while that of the conventional PLL was -78.4 dBc/Hz. The measured reference spur was also reduced from -38.7 dBc to -59.3 dBc. The proposed dual-loop PLL was fabricated in a 28-nm CMOS process. It occupies an area of 0.23 ㎟ and consumes 4 mW from a 1.0-V power supply when it operates at 1.5-GHz.

A Review on Power Supply Induced Jitter

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing

A layer of thick Cu metal is buried in the backside of a Si interposer and provides low resistivity and high capacitance for high-performance on-die power delivery networks (PDNs). The backside buried metal (BBM) layer can be as thick as $10 ~\mu \text{m}$ or even larger, and the stripes formed on the layer for interleaving power supply ( $V_{\mathrm {DD}}$ ) and ground ( $V_{\mathrm {SS}}$ ) wirings have large cross-sectional areas. The process flow developed for BBM is fully compatible with via-last type through-silicon via manufacturing. The Si interposer with BBM is stacked over an integrated circuit (IC) chip for improving PDN performance and suppressing power supply noise, as an over-the-top Si interposer (OVTT-SiIP). A test device of 65-nm CMOS digital IC chip and OVTT-SiIP was manufactured. The noise suppression ratio of 59.6% by the OVTT-SiIP technology is demonstrated by simulation with a full-chip PDN equivalent circuit network model and consistent with 49.7% by measurements on the test device with on-chip power noise monitoring function.

A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC

Abstract The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply Noise (PSN), along with dynamic and static power dissipation across the chip package. There have been several attempts to control this PSN; but it is the clock gating (CG) technique which is found to be efficient for the purpose. Though the primitive CG schemes are effective in managing the dynamic power dissipation, their performance to alleviate the static power and PSN is limited to certain extent. Therefore in this paper, we introduce a new and compact Data-Dependent CG (DD–CG) scheme which can possibly be the savior against both static and dynamic power as well as the PSN. The performance of the new DD–CG is tested over state-of-the-art master–slave flip-flop (MS–FF) and ISCAS’89 benchmark for 90 nm General Process Design Kit (GPDK) technology using the platform of Cadence Virtuoso® at supply voltage of 1.1 V and 5 GHz clock. It is observed that the new DD–CG based MS–FF smartly reduces the PSN individually by 22.19%, 18.99% and 46.92% in contrast to the prior-arts like NC2MOS–CG, LB–CG and no–gated peer. Accordingly, the static power is reduced by 20.63%, 17.79% and 33.61% and the dynamic power is also reduced by 25.14%, 21.24% and 61.57%. To justify the scalability of the design, we have also tested it for the lower process technologies like 65 nm, 40 nm and 28 nm UMC (United Microelectronics Corporation).

Blind Identification of Noisy Non-stationary Sources Using a Binary Mask

In most functional blind source separation (BSS) applications, the observations contain additive noise that limits the performance of most existing BSS algorithms, especially in the case where the noise is not modeled by a random process (e.g., electromagnetic power supply noise). In this paper, we describe an algorithm where a new cost function is fed with a frequency profile of the noise. In this way, the coefficients of the separating matrix are identified without the bias introduced by the noise. The proposed cost function is based on a frequency domain binary mask and the coherence function. The binary mask selects the frequencies where the signal-to-noise ratio (SNR) is relatively high, while the coherence is minimized to obtain the inverse system. Moreover, any frequency noise profile, whether given a priori or estimated, can be applied to the binary mask to achieve the identification of the inverse matrix. Computer simulations show that the proposed algorithm exhibits better performance under different SNR scenarios compared to methods developed previously.

Quick Prototyping Design for More than Moore era

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

A Resistorless High-Precision Compensated CMOS Bandgap Voltage Reference

A resistorless high-precision compensated CMOS bandgap voltage reference (BGR), which is compatible with a standard CMOS process, is presented in this paper. A higher-order curvature correction method called base-emitter voltage linearization is adapted to directly compensate the thermal nonlinearity of base–emitter voltage. With proper mathematical operations of high-order temperature currents, most of the nonlinear temperature terms in $V_{\mathrm {BE}}$ can be greatly eliminated. The proposed BGR, which is implemented in 0.35- $\mu \text{m}$ CMOS technology, is capable of working down to 2 V supply voltages with 1.14055 V mean output voltage. A minimum temperature coefficient of 1.01 ppm/°C with a temperature range from −40 °C to 125 °C is realized, and a power-supply noise attenuation of 61 dB is achieved without any filter capacitors. The line regulation is better than 2 mV/V from 2 V to 5 V supply voltage while dissipating a maximum supply current of $33~\mu \text{A}$ . The active area of the presented BGR is 180 $\mu \text {m}\times 220\,\,\mu \text{m}$ .