Power Delivery Network Modeling and Benchmarking for Emerging Heterogeneous Integration Technologies

Abstract

In this article, a power delivery network (PDN) modeling framework for heterogeneous integration platforms is presented, which includes both IR-drop and transient analysis. The model is validated using IBM power grid benchmarks, and maximum relative errors are less than 7.3%. To evaluate interposer and bridge-chip-based integration platforms, we assume a field-programmable gate array (FPGA)-CPU 2.5-D integration platform, of which the FPGA consumes 45 W and the CPU consumes 75 W. The simulation results show that an interposer with dense power/ground grid and microbumps can suppress power supply noise (PSN) by a small margin with the requirement of high-density through-silicon vias (TSVs). For bridge-chip-based integration, under the assumption that the active dice above the bridge-chips are not connected to the package power/ground planes, some PDN challenges are evaluated. Using multiple bridge-chips and smaller overlap areas between the bridge-chips and the active dice, the worst-case PSN in bridge-chip-based integration is minimized. Next, we perform parametric studies for these 2.5-D integration platforms as a function of C4 bump pitch and metal layers. Lastly, we propose to use TSVs in the bridge-chip to reduce PSN. With nine bundled TSVs of $8~\mu \text{m}$ diameter, the IR-drop of bridge-chip-based integration technologies is only 1% higher than the standalone case.