Power Supply Noise Research Articles

Channel Analysis for a 6.4 Gb s<sup>−1</sup> DDR5 Data Buffer Receiver Front-End

Abstract. In this contribution, the channel characteristic of the next generation DDR5-SDRAM architecture and possible approaches to overcome channel impairments are analysed. Because modern enterprise server applications and networks demand higher memory bandwidth, throughput and capacity, the DDR5-SDRAM specification is currently under development as a follow-up of DDR4-SDRAM technology. In this specification, the data rate is doubled to DDR5-6400 per IO as compared to the former DDR4-3200 architecture, resulting in a total per DIMM data rate of up to 409.6 Gb s−1. The single-ended multi-point-to-point CPU channel architecture in DDRX technology remains the same for DDR5 systems. At the specified target data rate, insertion loss, reflections, cross-talk as well as power supply noise become more severe and have to be considered. Using the data buffer receiver front-end of a load-reduced memory module, sophisticated equalisation techniques can be applied to ensure target BER at the increased data rate. In this work, the worst case CPU back-plane channel is analysed to derive requirements for receiver-side equalisation from the channel response characteristics. First, channel impairments such as inter-symbol-interference, reflections from the multi-point channel structure, and crosstalk from neighboring lines are analysed in detail. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. An architecture with 1-tap FFE in combination with a multi-tap DFE is proposed. Simulation of the architecture using a random input data stream is used to reveal the required DFE tap filter depth to effectively eliminate the dominant ISI and reflection based error components.

Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction

Tolerating timing error due to power supply noise (PSN) in digital circuits can be done with adding voltage margins. Conservative addition of voltage margins leads wastes of power reducing the battery life in Internet of Things (IoT) devices. This paper aims to provide guidelines to avoid over-design due to PSN especially for the low-cost IoT devices. To this end, we first present an accurate time-domain behavioral model of timing slack variation due to PSN accounting for the clock-data compensation. The accuracy of the model is verified against SPICE for complex designs, including AES engine and LEON3 processor. To prove the effectiveness of our model for reducing voltage margin, we utilize our model in standard VLSI design flow for various examples, such as timing slack versus noise frequency analysis, determining optimal value of an on-die capacitor, analyzing the effects of time borrowing technique, and PVT variation simulations. The analysis shows that the model helps reduce pessimism in estimated timing slack.

Zeroing of power supply noise sensitivity for ring oscillators operating from 1 to 4 GHz

A zeroing design for both positive and negative power supply noise sensitivities of the VCO to alleviate the jitter caused by the supply noise for the PLL operating over a range of 1–4GHz is proposed and demonstrated. The design uses a polarity check module to check the noise sensitivity polarity (positive or negative) of the supply noise. Then it uses a modified delay cell for which both its VDS and VGS can be adjusted to gain the bipolarity compensation. In addition, the calibration can be activated automatically when the PLL is locked or when the operating frequency is changed.

IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms

Power supply noise (PSN) is a growing concern in modern multiprocessor system-on-chips (MPSoCs). The advent of new architectures, such as the network-on-chip (NoC), the standard for on-chip communication in MPSoCs, has given rise to new challenges in maintaining reliable and energy-efficient operation. The growing NoC power footprint, increase in the transistor current, and high switching speed of the logic devices exacerbate the peak PSN in the NoC power delivery network (PDN). Hence, preserving power supply integrity in the NoC PDN is critical. In this paper, we propose IcoNoClast , a collection of a novel flow-control protocol (PAF) and an adaptive routing algorithm (PSN-aware routing), to mitigate the PSN in NoCs. Our best scheme achieves ~15% and ~12% improvements in the regional peak PSN and energy efficiency across a range of PARSEC benchmarks, with a 4.1% performance overhead and marginal area and power footprints.

Generating Current Constraints to Guarantee RLC Power Grid Safety

A critical task during early chip design is the efficient verification of the chip power distribution network. Vectorless verification, developed since the mid-2000s as an alternative to traditional simulation-based methods, requires the user to specify current constraints (budgets) for the underlying circuitry and checks if the corresponding voltage variations on all grid nodes are within a user-specified margin. This framework is extremely powerful, as it allows for efficient and early verification, but specifying/obtaining current constraints remains a burdensome task for users and a hurdle to adoption of this framework by the industry. Recently, the inverse problem has been introduced: Generate circuit current constraints that, if satisfied by the underlying logic circuitry, would guarantee grid safety from excessive voltage variations. This approach has many potential applications, including various grid quality metrics, as well as voltage drop-aware placement and floorplanning. So far, this framework has been developed assuming only resistive and capacitive (RC) elements in the power grid model. Inductive effects are becoming a significant component of the power supply noise and can no longer be ignored. In this article, we extend the constraints generation approach to allow for inductance. We give a rigorous problem definition and develop some key theoretical results related to maximality of the current space defined by the constraints. Based on this, we then develop three constraints generation algorithms that target the peak total chip power that is allowed by the grid, the uniformity of current distribution across the die area, and a combination of both metrics.

Enhancing the Bandwidth of Low-Dropout Regulators Using Power Transmission Lines for High-Speed I/Os

Power supply rejection peaking in low-dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. This paper presents a new design method by combining power transmission lines (PTLs) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high-speed I/O drivers. The PTL combined with decoupling capacitors on the package or board is used to mitigate the power supply noise (PSN). This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. Compared to conventional approaches, the PTL solution showed an ~80% lower PSN.

Nonorthogonal 2.5-D PEEC for Power Integrity Analysis of Package-Board Geometries

Design of the power ground layout of a multilayered printed circuit board (PCB) is crucial for low noise and stable power supply. 2.5-D tools are better suited for early stage power distribution network (PDN) analysis over 3-D full-wave electromagnetic solvers due to faster simulation times. For example, the multilayered finite difference method (MFDM), which is based on a 2.5-D formulation on an orthogonal mesh grid, can accurately model and analyze power planes. However, this method loses its advantage while analyzing planes with irregular shapes and holes, which require unnecessarily fine discretization at boundaries for a suitable staircase approximation in an orthogonal grid. In this paper, a nonorthogonal 2.5-D partial element equivalent circuit (PEEC) formulation is proposed, employing quadrilateral mesh elements for efficient simulation of the PDN. The individual stamps for resistance, inductance, capacitance, and conductance elements for a unit quadrilateral cell are derived. Further, the methodology is enhanced to capture coplanar coupling through the introduction of mutual inductance and capacitive terms between neighboring PEEC cell pairs. The numerical results demonstrate good accuracy compared with a 3-D full-wave commercial tool for layered PCB geometries. The efficiency of the proposed method is benchmarked against an orthogonal MFDM implementation and a commercial 2.5-D tool.

A Study of Reduction of Switching Power Supply Noise under Conducted Emission Noise Standard below 150kHz

A Study of Reduction of Switching Power Supply Noise under Conducted Emission Noise Standard below 150kHz

Integrated Thermal and Power Delivery Network Co-Simulation Framework for Single-Die and Multi-Die Assemblies

This paper presents a thermal and power delivery network (PDN) co-simulation framework for single-die and emerging multi-die configurations that incorporates the interactions between temperature, supply voltage, and power dissipation. The temperature dependencies of wire resistivity and leakage power are considered, and the supply voltage dependencies of power dissipation are modeled. Starting with a reference power dissipation, the framework is capable of evaluating the temperature distribution and PDN noise simultaneously and eventually updating the power dissipation based on the thermal and supply voltage distributions. The simulation results of an example two-tier 3-D stack show that prior models considering only part of the interactions between temperature, supply voltage, and power dissipation have a maximum error of 7.66%, 9.79%, and 4.64% in IR-drop, transient power supply noise, and temperature, respectively.

A Low Power, Low Noise Amplifier for Recording Neural Signals

The design of a low power amplifier for recording EEG signals is presented. The low noise design techniques are used in this design to achieve low input referred noise that is near the theoretical limit of any amplifier using a differential pair as input stage. To record the neural spikes or local field potentials (LFP’s) the amplifier’s bandwidth can be adjusted. In order to reject common-mode and power supply noise differential input pair need to be included in the design. The amplifier achieved a gain of 53.7dB with a band width of 0.5Hz to1.1 kHz and input referred noise measured as 357 nV<sub>rms </sub>operated with a supply voltage of 1.0V. The total power consumed is around 3.19µW. When configured to record neural signals the gain measured is 54.3 dB for a bandwidth of 100 Hz and the input referred noise is 1.04µ V<sub>rms</sub>. The amplifier was implemented in 180nm technology and simulated using Cadence Virtuoso.

Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited

Closed-form expressions to estimate power supply noise due to the simultaneous switching of I/O drivers are revisited in this brief. It is shown that existing closed-form expressions share a common limitation and underestimate noise with up to 83% error in advanced nanoscale technologies with fast signal rise/fall times. This characteristic is investigated, both quantitatively and qualitatively. New closed-form expressions are developed for the signals with fast transition times. Results demonstrate that the proposed closed-form expressions exhibit an average error of 3.3% as compared with SPICE simulations, and enhance the accuracy of the existing expressions by up to 79.4%.

PSN‐aware circuit test timing prediction using machine learning

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.

웨이브렛 변환의 모함수에 따른 ERG의 잡음제거 성능 비교

Purpose. Noise occurs at measuring Electoretinogram(ERG) signals as the other bio-signal measurement. It is compared the denoising performance according to the mother function of wavelet transforms. Methods. The ERG signal that generated power supply noise and white noise was used as a sampling signal. The noise of ERG signal was filtered by using haar, db7, bior mother function. The filtering performance of each mother functions was compared using Fourier transform spectrum and SNR(signal to noise ratio). Results. In the haar functioin, the result of the Fourier transform spectrum was that the power supply noise is removed and the white noise performance is not good. The SNR was 27.0404. In the db7 function, the results of Fourier transform spectrum was that the power supply noise is removed and the white noise performance is good. The SNR was 35.1729. In the db7 function, the results of Fourier transform spectrum was that the power supply noise is removed and the white noise performance is the bset. The SNR was 35.4445. Conclusions. The db7, bior function was good results in power supply noise and white noise filtered. The bior function is suitable for filtering noise of the ERG signal.

Design of Ultra-Low Noise and Low Temperature Usable Power System for High-Precision Detectors

In high-precision detector systems, the power supply usually need to be ultra-low noise and stabilized. Design and implementation of an ultra-low noise power supply is described in this paper. We implemented and tested the power system actually in a scientific CCD (Charge-coupled device) detector system, but the design structure could be used in many high-precision detector systems as infrared detector or high-energy particles detectors. The power system uses DC-DC switching regulators and LDO regulators for power generating, uses multi-stage filters for noise reducing. Multi-output power supply with noise about $40~\mu \text {V}_{\mathbf {rms}}$ is achieved, the overall energy efficiency is 68.5%. Besides, the electronic system takes the low temperature as an important consideration, and the system has been tested in an extreme environment as low as 193 K.

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.

Practical analysis of clock jitter reduction techniques under power supply noise for continuous-time delta-sigma modulators

Lowpass continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects and various techniques have been proposed to cope with them in the past years. While three major techniques...

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V reg for the BG core and Op-Amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.

Highly accurate capacitor‐free LDO with sub‐1 V −120 dB PSRR bandgap voltage reference

A low dropout (LDO) voltage regulator operated at 5 V power supply, along with a bandgap reference (BGR) voltage circuit with high power-supply rejection ratio (PSRR) is introduced. In the suggested LDO circuit, a low-pass filter for creating a common gate to transmit supply voltage to the power transistor gate is used. During deployment of the RC filter, an artificial resistor with a value of infinity is utilised, which in addition to reduce the chip occupied area, improves the performance of the low-pass filter at frequencies close to DC, and thus improves the PSRR at these frequencies. In addition, the high PSRR of the circuit is mediated by a low-voltage current mode regulator at the heart of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage ( V reg ) for BGR core and op-amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The circuit topology is discussed and simulation results are provided. The LDO is also stable without an output capacitor.

A Resistorless Low-Power Voltage Reference

A novel low-power temperature-stable voltage reference without resistors is presented in this brief, which is compatible with standard CMOS technology. In order to reduce the temperature nonlinearity in the proposed voltage reference, threshold voltage and a proportional-to-absolute-temperature voltage form the basic linear-temperature components, which are achieved by resistorless threshold voltage extractor and asymmetric differential difference amplifier. Moreover, a self-biased current source with feedback is used to provide stable bias currents for the whole voltage reference, which can improve the power-supply noise attenuation (PSNA) with reduced current mirror errors. Verification results of the proposed voltage reference implemented with 0.18- $\mu\text{m}$ CMOS technology demonstrate that the temperature coefficient of 14.1 ppm/°C with a temperature range of −20 °C to 80 °C is obtained at 1.35-V power supply, and a PSNA of 75.7 dB is achieved without any filtering capacitor while dissipating a maximum supply current of 880 nA. The active area is $115 \mu\text{m}\times 130 \mu\text{m}$ .

A novel Li-ion battery charger using multi-mode LDO configuration based on 350 nm HV-CMOS

The design of a novel Li-ion battery charger using multi-mode LDO architecture has been introduced in this paper. The proposed architecture, using an improved multi-mode LDO, not only obtains high accuracy but also reduces power supply noise because of utilizing novel error amplifier and power buffer configuration; while still consuming low power dissipation. To obtain the low power consumption, the Schmitt Trigger technique is applied to the charging controller and an optimized current driven circuit is proposed. Besides, the PSRR parameter is also enhanced by adding pre-regulation circuit in multi-mode LDO circuit. Thus, the proposed Li-ion battery charger achieves 700 mA operation current with 70.9 % efficiency but only dissipates 495 mW in power. During the charging process, the setting time and ripple issues are solved by the use of soft-start circuit which is integrated into the charging controller in order to decrease the chip area. Therefore, the setting time is reduced to 5.5 μs while gaining the load regulation at approximately 0.019 μV/mA and increasing PSRR up to 106 dB at DC level. Moreover, the line regulation is also reduced at 1.3 mV/V. The proposed linear battery charger is designed and implemented, based on High-Voltage CMOS process with using 4.5 V power supply voltage and obtaining 4.2 V battery output voltage.