Power Metal Oxide Semiconductor Field Research Articles

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

A leakage current is the most critical parameter to characterize heavy ion radiation damage in SiC MOSFETs. An accurate and refined analysis of the source and generation process of a leakage current is the key to revealing the failure mechanism. Therefore, this article finely tests the online and post-irradiation leakage changes and leakage pathways of SiC MOSFETs caused by heavy ion irradiation, analyzes the damaged location of the device in reverse, and discusses the mechanism of leakage generation. The experimental results further confirm that an increase in the leakage current of a device during heavy ion irradiation is positively correlated with the applied voltage of the drain, but the leakage path is not direct from the drain to the source. The experimental analysis of the source of the leakage current of the device after irradiation indicates that there is also a leakage current path between the device gate and source. The research results suggest that the experimental sample is more prone to a single-event gate rupture effect under this heavy ion radiation condition. The gate breakdown mainly occurs in the gate oxide layer at the neck region. This research can provide a theoretical basis for the radiation resistance reinforcement of SiC power devices.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Development of solderable layer on power MOSFET for double-side bonding

The use of power metal oxide semiconductor field effect transistor (MOSFET) packages is being actively explored to improve heat dissipation by fast switching. The double-side cooling package structure of power MOSFETs is considered efficient for heat dissipation, which requires bonding the MOSFET with Cu lead frames on both the top and bottom sides by soldering. Although soldering can typically be performed for the bottom side, it is challenging to perform on the top side due to Al metallization and has, therefore, been rarely reported. In this study, we developed various layers on the top side of a MOSFET to enable soldering between the MOSFET and Cu lead frame to realize a double-side cooling package. After depositing the thin films on the top side of the MOSFET with Ag and Ni materials, we fabricated the double-side package in the form of a TO-263 package to evaluate the electrical characteristics of the power MOSFET. In addition, we fabricated a typical TO-263 package having only the bottom-side cooling structure and compared its performance with that of the double-side cooling structure. Thermal cycle tests were performed up to 1500 cycles for 25 min at each extreme temperature in the −55 to 125 °C range. Electron backscatter diffraction was conducted on Al metallization beneath the solderable layers to analyze the change in the grain orientation and size of the Al layer. In addition, the stress behavior of the Al layer according to the presence of the Ni layer was compared using FEM simulation. Our findings provide the optimal solderable metallization of 600-nm-thick Ni and Ag layers each for bonding on the top layer of a power MOSFET, realizing a double-side cooling package for power MOSFETs.

3C-SiC-on-Si MOSFETs: Overcoming Material Technology Limitations

The cubic polytype (3C-) of silicon carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the wide band gap characteristics make it an excellent choice for power metal oxide semiconductor field effect transistors (<small>mosfet</small>s). It can be grown on silicon (Si) substrates which is itself advantageous. However, the allowable annealing temperature is limited by the melting temperature of Si. Hence, devices making use of 3C-SiC on Si substrate technology suffer from poor or even almost negligible activation of the p-type dopants after ion implantation due to the relatively low allowable annealing temperature. In this article, a novel process flow for a vertical 3C-SiC-on-Si <small>mosfet</small> is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with technology computer-aided design process and device software. To ensure reliable prediction, a previously validated set of material models has been used. Further, a channel mobility physics model was developed and validated against experimental data. The output characteristics of the proposed device demonstrated promising performance, what is potentially the solution needed and a huge step toward the realization of 3C-SiC-on-Si <small>mosfet</small>s with commercially grated characteristics.

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Reliability analysis for TO-247 multilayered power module packaging under mechanical oscillation based on finite element method

This paper presents the simulation and hardware test results for determining the fatigue life of the solder joints of a printed circuit board (PCB) including a DC to AC inverter circuit with six power metal oxide semiconductor field effect transistors (MOSFETs) by using the finite element method (FEM) under different vibration effects. This board is exposed under different angles by a vibration machine. The selected angles were performed on the power module to find the maximum stress points of the power module for different vibration frequencies. The results indicate that the maximum stress is observed at the corners of the solder layer. The stress of the solder joints significantly increases when the input frequency increases, and the failure, voids generation and crack formation and propagation are more observable under this condition. Furthermore, the loading direction changes show that the peeling stress of the solder layer is directly affected by lower angles. The shear stress occurs in lower angles of loading directions, and this situation results in the peeling stress. The simulation investigations are proved by the experimental results in the study. According to the observations, the fatigue effects result in the coalescence and the void growths in lower angles of vibration loadings. The paper also investigates the normal loading condition of the power inverter circuit, and the highest reliability is obtained compared to all other experimental tests.

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop to be stable. The proposed compensator has miller compensation along with AFFC which helps to eliminate the minimum load demand for the feedback-loop of the LDO to be stable by shifting the right half-plane (RHP) zero of power MOSFET to left half-plane (LHP) zero. This LHP zero proportionally varies with the first non-dominant pole at the output of the LDO as the load current varies from light load to heavy load and extends the unity gain frequency of the proposed LDO. The SRE circuit supports fast load transients with edge time of 50 ns and achieves less voltage spike without consuming any power at steady-state. This LDO is implemented in 0.18 μ m technology with a drop-out voltage of 200 mV and can drive the load current range of 0–50 mA with regulated output voltages from 1.2 to 1.6 V. It settles faster with the settling time of 250 ns and has the quiescent current of 25.8 μ A .

A Bidirectional Communicating Power Supply Circuit for Smart Gate Driver Boards

In power circuits, the gate drivers are required to provide an optimal and safe switching of power semiconductor devices. Nowadays, the gate driver boards include more and more features, such as short-circuit detection, soft-shutdown, temperature sensing, on-state voltage monitoring. Research works are in progress on the integration of on-line monitoring features for a predictive maintenance. The instrumentation of the gate drive system supposes the integration of a communication system to transmit the monitoring data. In high-power designs, a galvanic isolation is mandatory on the gate driver board. The parasitic capacitance seen on the isolation barrier is critical in these designs as it can lead to the circulation of common mode currents during the switching. Adding extra optocouplers or transformers on the isolation barrier is, therefore, risky due to electromagnetic interference constraints. In this article, a new bidirectional data transmission method is proposed for gate drivers used for driving 1.2 kV silicon carbide (SiC) power metal oxide semiconductor field effect transistors (mosfets). The proposed method enables the energy transmission and a bidirectional data exchange on a single power supply transformer. The experimental results are provided demonstrating 1 Mb/s for TxD and 16 kb/s for RxD. The targeted application is the health monitoring of SiC power mosfets using the gate driver board.

All SiC PWM rectifier‐based off‐board ultrafast charger for heavy electric vehicles

本研究涉及用于重型电动汽车钛酸锂电池的基于全碳化硅脉宽调制 (SiC PWM) 整流器的非车载超快充电器 (UFC) 的设计、实现和实验性能。根据标称电池电压（400–1000 V DC）和充电容量，建议使用不同的 UFC 配置。评估了UFC在单位功率因数和超前功率因数下的工作原理和控制，并讨论了PWM整流器的相应工作模式。在进行的所有分析中都考虑了 SiC 功率金属氧化物半导体场效应晶体管 (MOSFET) 和内置 SiC 肖特基二极管的反向传导特性的组合效应。开发的 UFC 的工作性能，例如 SiC 功率 MOSFET 模块的开关特性、效率、输入电流总需求失真 (ITDD) 和 SiC PWM 整流器的热限制已经针对各种充电电压和充电容量进行了评估，两者都通过计算机模拟和实验室测试。本研究还给出了建议系统的电源电路布局考虑因素。开发的 200 kW UFC 在 10 kHz 开关频率下获得了出色的性能结果，在高达电池容量五倍的所有充电率下运行效率高于 98.5%，并且在整个运行范围内 ITDDs <2.2%。

Threshold Voltage Degradation for n-Channel 4H-SiC Power MOSFETs

In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices to determine electrical parameters’ degradations. This work proposes an experimental procedure to characterize silicon carbide (SiC) power MOSFETs following two characterization methods: (1) Using the one spot drop down (OSDD) measurement technique to assess the threshold voltage explains temperature dependence when used on devices while they are subjected to high temperatures and different gate voltage stresses. (2) Measurement data processing to obtain hysteresis characteristics variation and the damage effect over threshold voltage. Finally, based on the results, it was concluded that trapping charge does not cause damage on commercial devices due to reduced value of recovery voltage, when a negative small voltage is applied over a long stress time. The motivation of this research was to estimate the impact and importance of the bias temperature instability for the application fields of SiC power n-MOSFETs. The importance of this study lies in the identification of the aforementioned behavior where SiC power n-MOSFETs work together with complementary MOS (CMOS) circuits.

Investigation of the Thermal Loading and Random Vibration Influences on Fatigue Life of the Solder Joints for a Metal-Oxide-Semiconductor-Field-Effect Transistor in a DC-DC Power Boost Converter

This study presents the effects of the vibration and thermal cycling on the fatigue life of a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in a power converter circuit. The fatigue mechanism in per loading mode was investigated separately and based on the overlap approach, the synchronous effects were analyzed. The solder creeps’ attitudes are depended on the fatigue life for the thermal loops. The success of the deposited strain per thermal loop is in direct relation with the fatigue lifetime. The main source of the stress in the packaging process is the differences between the components’ thermal coefficients. To evaluate the effects of the vibration on the fatigue life for the solder layers, the RMS value of the peeling stress was considered. According to the results, the maximum stress and main affected points realized at the corners of the layers. It has been identified that the assembling of the thermal effects and mechanical loads are quickened the failure rate at the solder joints for this device. The Finite Element Method (FEM) is used for the simulation and the results confirm the estimated crack formation places in the layers.

Simulation study of single event effects sensitivity on commercial power MOSFET with single heavy ion radiation

High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.

EMI mitigation in switching power converters combining closed‐loop gate drive and chaotic frequency modulation technique

All switching power converters are characterised by inevitable switching actions with relevant interference emissions. The voltage and current transients of power metal oxide semiconductor field effect transistor (MOSFET)/insulated-gate bipolar transistor are the main sources in switching power converters for both conducted and radiated emissions. In this study, a promising electromagnetic interference (EMI) mitigation method combining the closed-loop gate drive method and the chaotic switching frequency modulation technique is demonstrated for switching power converters. A chaotic pulse-width modulation waveform with Gaussian S-shape switching transients was proposed to achieve remarkable reduced EMI generation at all frequencies. Spectral characteristics of this new switching waveform were investigated by the power spectral density to verify the feasibility of reduced EMI generation. A closed-loop gate controller was presented to shape the switching transients of power MOSFET into the proposed switching waveform. Circuit tests were carried out in both simulations and experiments. The results validated that the proposed method could achieve remarkable EMI mitigation in switching power converters.

Implementation of a soft switching converter with series DC–DC circuits and single transformer

A high efficiency converter is developed for high-voltage input and low-voltage output such as DC light rail vehicle, industry high power units with three-phase AC input or bipolar DC micro-grid system. The proposed circuit structure is constructed with series DC–DC circuits to lessen voltage rating of power metal oxide semiconductor field effect transistors (MOSFETs). Single transformer is employed with two primary inputs and one secondary output to lessen conduction loss on power MOSFETs and copper loss on transformer windings so that the converter efficiency is improved. Phase-shift duty cycle control is employed to reduce switching loss on MOSFETs. Input voltages balance problem in conventional three-level converters is overcome by using a voltage balance capacitor. The effectiveness and feasibility of the studied structure were evaluated based on 1 kW DC converter with 100 kHz switching frequency.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time. The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs. Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation. The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation. The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions. The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs. The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage. In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound).

Oscillation analysis and current peak reduction in paralleled SiC MOSFETs

Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.

Low-power CMOS integrated current sensor for current-mode DC-DC buck converter

PurposeThis paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.Design/methodology/approachThe integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.FindingsExperiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.Originality/valueThe proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

Study the Effects of Photon Radiation on Power MOSFET for Harsh Environment Application

The rapid growth of the advanced technologies in power electronics system gives a challenge to the electronic device to sustain with the modern technologies nowadays. The challenges are also including the place where the system was installed for example the application in the harsh environment. Harsh environment application requires an electronic device deals with radiation pollution. Hence, the electronic device will suffer from this phenomenon and make the whole system to malfunction and break down. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of electronic device that is the most broadly for high voltage and high switching speed application. The aim of this paper is to studies the photon radiation effect toward the Power MOSFET performance. The study focus on the changing of the electrical characteristics of the device after radiated with photon radiation. Process simulation and Device simulation tools in Sentaurus Synopsys Software used for the research to validate all the theory.