Abstract
The cubic polytype (3C-) of silicon carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the wide band gap characteristics make it an excellent choice for power metal oxide semiconductor field effect transistors (<small>mosfet</small>s). It can be grown on silicon (Si) substrates which is itself advantageous. However, the allowable annealing temperature is limited by the melting temperature of Si. Hence, devices making use of 3C-SiC on Si substrate technology suffer from poor or even almost negligible activation of the p-type dopants after ion implantation due to the relatively low allowable annealing temperature. In this article, a novel process flow for a vertical 3C-SiC-on-Si <small>mosfet</small> is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with technology computer-aided design process and device software. To ensure reliable prediction, a previously validated set of material models has been used. Further, a channel mobility physics model was developed and validated against experimental data. The output characteristics of the proposed device demonstrated promising performance, what is potentially the solution needed and a huge step toward the realization of 3C-SiC-on-Si <small>mosfet</small>s with commercially grated characteristics.
Highlights
Silicon Carbide (SiC) is a wide band gap (WBG) semiconductor material with superior material characteristics compared to silicon (Si)
Synopsys Sentaurus Device [31] tool has been used to simulate the electrical performance of the proposed structures (Fig. 3)
P-stripes exist in the JFET, which obstruct the free electron flow, resulting in a non-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) structure characterized by an excessive resistance value
Summary
Silicon Carbide (SiC) is a wide band gap (WBG) semiconductor material with superior material characteristics compared to silicon (Si). Due to the narrower bandgap energy window of 3C-SiC, the majority of the observed SiO2/SiC interface trap are energetically located in the conduction band (EC), essentially improving the effective channel mobility [8]–[11] Both vertical and lateral 3C-SiC-on-Si power MOSFETs have been developed and characterized in the literature [12]– [17]. They are not commercialized yet because of the high planar defects density in the 3C-SiC grown layers originating from the hetero-interface to Si during growth [18]. Such inefficient holes’ generation process demands high acceptor dopant concentration for p-type 3C-SiC which in turn induces more lattice defects deteriorating the hole mobility This challenge can be a limiting factor for conventional 3C-SiC-on-Si MOSFET designs. The results in this work highlight that the proposed design is able to deliver 3C-SiCon-Si MOSFETs with excellent output characteristics
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