Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit

Abstract

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop to be stable. The proposed compensator has miller compensation along with AFFC which helps to eliminate the minimum load demand for the feedback-loop of the LDO to be stable by shifting the right half-plane (RHP) zero of power MOSFET to left half-plane (LHP) zero. This LHP zero proportionally varies with the first non-dominant pole at the output of the LDO as the load current varies from light load to heavy load and extends the unity gain frequency of the proposed LDO. The SRE circuit supports fast load transients with edge time of 50 ns and achieves less voltage spike without consuming any power at steady-state. This LDO is implemented in 0.18 μ m technology with a drop-out voltage of 200 mV and can drive the load current range of 0–50 mA with regulated output voltages from 1.2 to 1.6 V. It settles faster with the settling time of 250 ns and has the quiescent current of 25.8 μ A .