Power Gating Method Research Articles

F-Bypass: a low-power network-on-chip design utilizing bypass to improve network connectivity

With the development of transistor feature size to nanometer level, static power consumption has gradually become the main factor affecting the overall power consumption of network on chip (NoC). Power gating is an effective technology to reduce static power consumption, but it also brings new challenges, such as BET violation, wake-up latency and network connectivity. Therefore, a power gating method is needed to improve NoC performance and reduce static power consumption. This paper proposes a low-power bypass method, namely Forwarding bypass (F-Bypass). First, F-Bypass adds bypass paths between all input and output ports and the network interface (NI), and connects the pop-up port and injection port in NI through the bypass path. When the router is powered off, F-Bypass performs wake-up-free packet transmission, which reduces the break-even time (BET) violation and cumulative wake-up latency while ensuring network connectivity. Secondly, This paper add the modified VC state table to NI, so that the power-off router can perform normal traffic control. Finally, a new wake-up criterion is proposed, which can effectively avoid the frequent wake-up of power-off routers, and the detailed hardware implementation of F-Bypass is provided.The simulation results under integrated traffic load show that compared with the traditional scheme, the delay of F-Bypass is reduced by 2.2%, the throughput is increased by 13.1%, and the total static power consumption is reduced by 75.2%. Key performance indicators are superior to other solutions, and the increased area cost is moderate.

Applying SMART-Based Power Gating Approach in NoC System

SMART is a low-latency solution that transmits nonconflicting flits to remote routers, enabling traversal of multi-hop paths within a single cycle. It reduces packet latency but ignores high power consumption in idle components. Additionally, SMART’s low latency is highly dependent on [Formula: see text], which represents the maximum number of hops traversed within a cycle. Therefore, this paper presents SMART-PG, a power gating method based on SMART that reduces network power consumption by shutting down idle components such as router buffers under low-load conditions. We also extend the router architecture to enable the continuous establishment of single-cycle multi-hop bypass paths. Compared to SMART routers, our method eliminates packet buffering even when a packet reaches the last router of a single-cycle multi-hop path, reducing packet latency and sensitivity to [Formula: see text]. Finally, we propose a routing algorithm that enables efficient packet transmission in one-dimensional and two-dimensional networks even when routers are powered off. Experimental results show that our method reduces packet latency and static power consumption by an average of 7.5% and 46.4%, respectively, compared to the baseline router. Compared to SMART routers, our method demonstrates significant superiority in terms of packet latency and the impact of multi-hop length on packet latency.

FinFET based SRAM cells design in various topologies using different power reduction techniques

<p>In Very Large Scale Integration (VLSI) design, device scaling is restricted due to subthreshold swing limitations and short channel effects. This article discusses the role of different power reduction techniques in the implementation of 14 nm fin-shaped field-effect transistor (FinFET) centered static random access memory (SRAM) cells with good subthreshold swing and reduced short channel effects (SCE). Dynamic threshold and power gating are incorporated in SRAM cells to advance the memory cell performance by reducing static power dissipation in standby mode. The power analysis was performed on different SRAM cells with different transistor count i.e., 6, 7, 8, and 9. The performance of SRAM cell is analysed in power dissipation and is reduced by 20% using power gating method and in dynamic threshold it is reduced to nano watts due to less leakage power.</p>

A transparent virtual channel power gating method for on-chip network routers

Since static power gradually dominates on-chip network power, power gating has been widely studied as a way to mitigate this trend. Even though many power gating methods reduce static power, they introduce new problems such as higher latency and hardware overhead, network disconnections, and low scalability. A new power gating method is therefore needed that can effectively reduce static power without sacrificing the benefits of the on-chip network. In this paper, we propose an efficient power gating method for virtual channels. Firstly, neighboring routers no longer exchange and store each other’s power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads. Secondly, in order to eliminate flit stalls and reduce network latency, we propose a modified credit-based flow control and provide a detailed hardware implementation. Finally, bypasses allow packets to reach processing elements (PEs) or downstream routers without waking up sleeping virtual channels, which reduces breakeven time (BET) violations and cumulative wake-up latency while ensuring network connectivity. Based on the evaluation, under real applications, the proposed power gating method reduces static energy by an average of 82.5% compared to the baseline, while increasing latency overhead by 13.7% and area overhead by 6.48%.

Reducing GPU Energy Consumption by Packing Narrow-Width Operands

In this paper, we study the use of an Operand-Width-Aware Register (OWAR) packing mechanism for graphics processing unit (GPU) energy saving. In order to efficiently use the GPU register file (RF), OWAR employs a power gating method to shut down unused register sub-arrays in order to reduce dynamic and leakage energy consumption of RF. As the number of register accesses was reduced due to the packing of the narrow width operands, the dynamic energy dissipation was further decreased. Finally, with the help of RF usage optimized by register packing, OWAR allowed GPUs to support more thread-level parallelism (TLP) through assigning additional thread blocks on streaming multiprocessors (SMs) for general-purpose GPU (GPGPU) applications that suffered from the deficiency of register resources. The extra TLP opens opportunities for hiding more memory latencies and thus reducing the overall execution time, which can lower the overall energy consumption. We evaluated OWAR using a set of representative GPU benchmarks. The experimental results showed that compared to the baseline without optimization, OWAR can reduce the GPGPU’s total energy up to 29.6% and 9.5% on average. In addition, OWAR achieved performance improvement up to 1.97X and 1.18X on average.

NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design

Power dissipation has become a major concern in nanoscale integrated circuits. The power gating and dual-supply design methods are among the most effective approaches for reducing the static and dynamic power consumptions. However, these methods require efficient data retention and voltage level conversion. In this paper, a nonvolatile level converter flip-flop (NVLCFF) is proposed to be used in ultra-low-power integrated circuits. Our proposed NVLCFF employs the magnetic tunnel junction (MTJ) for data retention. Spin transfer torque along with the spin Hall effect is used for reconfiguring the MTJs. The peripheral circuitry is designed using 7-nm FinFET as one of the leading industrial technologies. Furthermore, to facilitate the use of the dual-supply approach, voltage level conversion is performed in the structure of the proposed NVLCFF. According to the HSPICE simulations, the power consumption, backup energy and restore energy of the proposed circuit are on average 59%, 48% and 92% lower than the other NVLCFFs based on the previous nonvolatile flip-flops with different MTJ structures. Furthermore, the comprehensive Monte Carlo simulations indicate the robustness of the proposed design in the presence of major MTJ and FinFET process variations as compared to the previous designs.

Leakage Power Reduction by Using Power Gating Methods in Differential Amplifier

Leakage Power Reduction by Using Power Gating Methods in Differential Amplifier

Evaluation of Energy Efficient High Performance Power Gated Programmable Logic Array’s Under 65 nm Process Technology

The Programmable Logic Array (PLA) forms the major building block in the implementation of sequential and combinational functionalities in VLSI based embedded systems. Increased sub threshold leakage current resulting from the scaling down of the microprocessors carrying PLA causes high power dissipation. In order to improve the energy consumption of future electronic products, we propose a power gating method involving sleepy modes at transistor level implemented using 65 nm technology. This paper describes the design and analysis of PLA’s with footer switches for power gating. A comparative analysis has been made between the AND array, OR array and the inverter elements of the proposed PLA’s and the conventional one. Results produced through simulation confirms an optimized power reduction and the transient analysis of the proposed PLA models is proved to be much better than the conventional PLA.

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling

Dynamic Voltage and Frequency Scaling is the most commonly used power managment techinique in modern processors. However, the ability of an individual chip to operate under reduced supply voltage can no longer be predetermined at the design stage and may even change over time. This paper presents Cyclic Power-Gating (CPG), a novel power management strategy where the power consumption of a core can be finely controlled without scaling the supply voltage. CPG builds on state-retentive power-gating which allows the power supply to a core to be switched off and on again at high speed (tens of clock cycles) with minimal disruption to running programs. The power-gating is cyclic, by altering the ratio of time spent powered-on and off in each power-gating period the effective operating frequency and power consumption of a core can be controlled. The overheads in delay and power consumption of CPG for an out-of-order core in a 14 nm technology are accurately modelled and compared to the performance and power consumption of Voltage/Frequency pairs in the same technology. The proposed power gating method reduces average power consumption by 4 percent over voltage and frequency scaling with only a 2 percent degradation in performance.

Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method

Performance Analysis of CMOS Circuit by Using Sub Clock Power Gating Method

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been widely used to reduce the standby leakage energy. In this work, we investigate a power-gating strategy for through-silicon via (TSV)-based 3D IC stacking structures. Power-gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC to perform power-gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power-gating strategy that optimizes the in-rush current profile, subject to the voltage-drop constraints. Our power-gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating is analyzed in terms of the wake-up time reduction. We achieve an average wake-up time reduction of 43% for all cases with our adaptive power-gating method that exploits location (or layer) information regarding the aggressors in a 3D IC. A tapered TSV architecture based on the layer dependency has been analyzed; it exhibits up to 18% wake-up time reduction compared to that of circuits with uniform TSVs.

A Dynamic Instrumentation Amplifier for Low-Power and Low-Noise Biopotential Acquisition

A low-power and low-noise dynamic instrumentation amplifier (IA) for biopotential acquisition is presented. A dynamic IA that can reduce power consumption with a timely piecewise power-gating method, and noise level with an alternating input and chopper stabilization technique is fabricated with a 0.13-μm CMOS. Using the reconfigurable architecture of the IA, various combinations of the low-noise schemes are investigated. The combination of power gating and chopper stabilization shows a lower noise performance than the combination of power gating and alternating input switching scheme. This dynamic IA achieved a power reduction level of 50% from 10 µA to 5 µA and a noise reduction of 90% from 9.1 µVrms to 0.92 µVrms with the combination of the power gating and chopper stabilization scheme.

POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

Power Gating Method for Power Supply Noise Suppression

As technology scaling down, power consumption of integrated circuits increases tremendously due to leakage current. Power gating is one of the most effective techniques to reduce leakage power by shutting off idle blocks from power supply. However, during a power-mode transition, an instantaneous charge current passes through the switch transistor, and creates current surge elsewhere. Because of the self-inductance of the off-chip bonding wires and parasitic inductance inherent to the on-chip power rails, these surges result in severe simultaneous switching noise (SSN), which results in function failure.Based on typical power delivery network, it is found that the magnitude of SSN would accumulate positively with Fcurrent = 1/(n + 1) Resonant, and the magnitude of SSN would accumulate negatively with Fcurrent = 1/(n + 1/2) Resonant. In this paper, a new method is proposed to suppress the power supply noise based on its periodic characteristic. By cutting power grid, partition of switch transistors and controlling their switching, smaller segmented charge current magnitude and controllable period can be provided into gated block for mitigating noise. The power supply noise produced by charge current can be suppressed through adjusting the delay of charge current and the magnitude of charge current which is verified by simulation. Compared to conventional power gating structures, this method can save decap area and is practical and flexible to embed in an optimization flow. A principle for controllable switch transistor chain is also given to simplify the high speed power delivery network design.

A Low-Power Block-Based CMOS Image Sensor With Dual VDD

A novel low-power image sensor with dual analog power supply 1.8 and 1.1 V during image capture stage is proposed. Different from a traditional imager having a unique analog power for image capture, the proposed imager works on blocks of 8 × 8 pixels and the power supply for each block is selected according to the estimated variance inside the block. For the blocks with large variance, high supply voltage will be chosen to achieve high imaging performance; otherwise, low supply voltage will be used to save power. In addition, the power gating method is applied to the additional computation circuits to save power further. Theoretical analysis and simulation results by Matlab and Cadence are given to demonstrate the efficiency of the proposed methodology. The amount of power saved by the proposed imager varies from image to image. Theoretically, up to 37% of power can be saved for images with predominant background, while no noticeable quality degradation of the reconstructed pictures after compression and decompression is perceived (PSNR reduced by less than 1.5 dB). The chip is implemented in TSMC 0.18 μm CMOS technology and simulated by Spectre Cadence. The total power consumption of the additional computation logic is only about 7.0 μW .

Power gating strategies on GPUs

As technology continues to shrink, reducing leakage is critical to achieving energy efficiency. Previous studies on low-power GPUs (Graphics Processing Units) focused on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage and Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecture-level power gating techniques for leakage reduction on GPUs. We propose three strategies for applying power gating on different modules in GPUs. The Predictive Shader Shutdown technique exploits workload variation across frames to eliminate leakage in shader clusters. Deferred Geometry Pipeline seeks to minimize leakage in fixed-function geometry units by utilizing an imbalance between geometry and fragment computation across batches. Finally, the simple time-out power gating method is applied to nonshader execution units to exploit a finer granularity of the idle time. Our results indicate that Predictive Shader Shutdown eliminates up to 60% of the leakage in shader clusters, Deferred Geometry Pipeline removes up to 57% of the leakage in the fixed-function geometry units, and the simple time-out power gating mechanism eliminates 83.3% of the leakage in nonshader execution units on average. All three schemes incur negligible performance degradation, less than 1%.

Fine-Grained FSMD Power Gating Considering Power Overhead

As a fine-grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD-based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned-on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.

Low power finite state machine synthesis using power-gating

Power-gating turns off the power supply of a portion of the circuit completely, resulting in total elimination of power consumption for that part. However, it also necessitates that the sub-circuit to be activated should be charged for some time before its activation. This critical issue can influence the decomposition of a finite state machine (FSM) for its power gated implementation. In this paper we have presented a power-gating method that integrates FSM partitioning with state encoding, thus providing a total solution to the problem of power-aware FSM synthesis. It shows better results, in terms of dynamic and leakage power consumption, compared to the existing techniques reported in the literature.

Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity

In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.