A transparent virtual channel power gating method for on-chip network routers

Abstract

Since static power gradually dominates on-chip network power, power gating has been widely studied as a way to mitigate this trend. Even though many power gating methods reduce static power, they introduce new problems such as higher latency and hardware overhead, network disconnections, and low scalability. A new power gating method is therefore needed that can effectively reduce static power without sacrificing the benefits of the on-chip network. In this paper, we propose an efficient power gating method for virtual channels. Firstly, neighboring routers no longer exchange and store each other’s power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads. Secondly, in order to eliminate flit stalls and reduce network latency, we propose a modified credit-based flow control and provide a detailed hardware implementation. Finally, bypasses allow packets to reach processing elements (PEs) or downstream routers without waking up sleeping virtual channels, which reduces breakeven time (BET) violations and cumulative wake-up latency while ensuring network connectivity. Based on the evaluation, under real applications, the proposed power gating method reduces static energy by an average of 82.5% compared to the baseline, while increasing latency overhead by 13.7% and area overhead by 6.48%.