Efficient virtual channel allocator for NoC router micro-architecture

Abstract

Low-level design parameters such as router micro-architecture (RMA), flow controls (resource allocation), routing techniques and traffic patterns have a major significance on cost and performance of Network on Chip (NOC) design. This work proposes an efficient virtual channel (VC) buffer management structure and a dynamic VC allocation mechanism for the router to minimize latency, and area (buffer allocation) overhead. The proposed VC architecture and allocation algorithm can be adapted to various switching techniques used in NoC implementations with buffers and is independent of the topology. The architecture was developed and simulated for various traffic patterns. The performance was evaluated for different load scenarios and comparison to existing VC allocation algorithms are discussed in this paper. Our implementation achieves better performance (throughput and area overhead) compared to baseline and Adaptive Backpressure (ABP) VC allocation algorithm.