Latency Improvement by Using Fill VC Allocation for Network on Chip

Abstract

Network on Chip (NoC) is gaining popularity as an interconnect structure for complex multicore system on chip. The overall performance of NoC can be enhanced by improving latency, power consumption and throughput. The virtual channel (VC) allocation mechanism takes into consideration the buffer utilization which in turn improves the overall performance of NoC. In this paper, Fill VC allocation mechanism is proposed which reduces the number of pipeline stages. The proposed method is implemented in Booksim and the results show that the average packet latency is reduced by 58.57%, 16.66% and 36.66% for uniform, bitrev and tornado traffic, respectively, over conventional VC router for the mesh network. Also for flattened butterfly, the reduction in average packet latency is 56.66% and 62.5% as compared to conventional VC router for tornado and transpose traffic, respectively. Also, the real-time applications of NoC where massive data flow occurs are listed. VC allocation plays a critical role in such cases in deciding the overall performance of NoC.