FinFET based SRAM cells design in various topologies using different power reduction techniques

Abstract

<p>In Very Large Scale Integration (VLSI) design, device scaling is restricted due to subthreshold swing limitations and short channel effects. This article discusses the role of different power reduction techniques in the implementation of 14 nm fin-shaped field-effect transistor (FinFET) centered static random access memory (SRAM) cells with good subthreshold swing and reduced short channel effects (SCE).  Dynamic threshold and power gating are incorporated in SRAM cells to advance the memory cell performance by reducing static power dissipation in standby mode. The power analysis was performed on different SRAM cells with different transistor count i.e., 6, 7, 8, and 9. The performance of SRAM cell is analysed in power dissipation and is reduced by 20% using power gating method and in dynamic threshold it is reduced to nano watts due to less leakage power.</p>