Single-Port SRAM Cell with lower leakage current in standby mode

Abstract

As is known in the art, it is relatively difficult to write a logic ‘1’ to the five-transistor (5T) static random access memory (SRAM) cell if the SRAM cell currently stores a logic ‘0’. In this paper, we proposed a 5T SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the HVDD supply voltage if the SRAM cell is in a read mode. If the SRAM cell is being written or during a standby mode, the cell voltage control circuit supplies the SRAM cell with the LVDD supply voltage that is less than the HVDD supply voltage. Several HSPICE simulations show that the proposed SRAM cell provides an improvement in SRAM cell topology by providing an efficient solution to the write ‘1’ issue.